TMS320TCI6602 Datasheet, PDF (140/201 Pages) Texas Instruments – Multicore Fixed and Floating-Point Digital Signal Processor

TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Table 7-38 TPCC2 Events for TCI6602 (Part 2 of 2)
Event Number
Event
Event Description
59
INTC2_OUT39
Interrupt controller output
60
INTC2_OUT40
Interrupt controller output
61
INTC2_OUT41
Interrupt controller output
62
INTC2_OUT42
Interrupt controller output
63
End of Table 7-38
INTC2_OUT43
Interrupt controller output
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7.10 Interrupts
7.10.1 Interrupt Sources and Interrupt Controller
The CPU interrupts on the TCI6602 device are configured through the C66x CorePac Interrupt Controller. The
interrupt controller allows for up to 128 system events to be programmed to any of the twelve CPU interrupt inputs
(CPUINT4 - CPUINT15), the CPU exception input (EXCEP), or the advanced emulation logic. The 128 system
events consist of both internally-generated events (within the CorePac) and chip-level events.
Additional system events are routed to each of the C66x CorePacs to provide chip-level events that are not required
as CPU interrupts/exceptions to be routed to the interrupt controller as emulation events. Additionally, error-class
events or infrequently used events are also routed through the system event router to offload the C66x CorePac
interrupt selector. This is accomplished through INTC blocks, INTC[2:0], with one controller per C66x CorePac.
This is clocked using CPU/6.
There are a large amount of events on the chip level. The chip level INTC provides a flexible way to combine and
remap those events. Multiple events can be combined to a single event through chip level INTC. However, an event
can only be mapped to a single event output from the chip level INTC. The chip level INTC also allows the software
to trigger system event through memory writes. The broadcast events to C66x CorePacs can be used for
synchronization among multiple cores or inter-processor communication purpose and etc. For more details on the
INTC features, please refer to the Interrupt Controller (INTC) for KeyStone Devices User Guide (literature number
SPRUGW4).
Note—Modules such as CP_MPU, CP_Tracer, and BOOT_CFG have level interrupts and EOI handshaking
interface. The EOI value is 0 for CP_MPU, CP_Tracer, and BOOT_CFG.
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