TMS320TCI6602 Datasheet, PDF (141/201 Pages) Texas Instruments – Multicore Fixed and Floating-Point Digital Signal Processor

TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
www.ti.com
SPRS782A—August 2011
Figure 7-33 shows the TCI6602 interrupt topology.
Figure 7-33 TMS320TCI6602 Interrupt Topology
5 Reserved Secondary Events
91 Core-only Secondary Events
64 Common Events
INTC0
8 Broadcast Events from INTC0
71 Primary Events
17 Secondary Events
Core0
71 Primary Events
17 Secondary Events
Core1
64 Common Events
8 Reserved Secondary Events
88 TPCC-only Events
INTC2
2 Reserved Secondary Events
38 Primary Events
26 Secondary Events
CPU/3
TPCC1
40 Primary Events
24 Secondary Events
CPU/3
TPCC2
17 Reserved Secondary Events
63 Events
INTC3
32 Queue Events
32 Secondary Events
8 Primary Events
8 Secondary Events
Hyper
Link
CPU/2
TPCC0
Table 7-39 shows the mapping of system events. For more information on the Interrupt Controller, see the C66x
CorePac User Guide (literature number SPRUGW0).
Table 7-39 TMS320TCI6602 System Event Mapping — C66x CorePac Primary Interrupts (Part 1 of 4)
Event Number
Interrupt Event
Description
0
EVT0
Event combiner 0 output
1
EVT1
Event combiner 1 output
2
EVT2
Event combiner 2 output
3
EVT3
4
TETBHFULLINTn ⁽¹⁾
5
TETBFULLINTn ⁽¹⁾
6
TETBACQINTn ⁽¹⁾
7
TETBOVFLINTn ⁽¹⁾
8
TETBUNFLINTn ⁽¹⁾
Event combiner 3 output
TETB is half full
TETB is full
Acquisition has been completed
Overflow condition interrupt
Underflow condition interrupt
9
EMU_DTDMA
10
MSMC_mpf_errorn ⁽²⁾
ECM interrupt for:
1. Host scan access
2. DTDMA transfer complete
3. AET interrupt
Memory protection fault indicators for local core
11
EMU_RTDXRX
RTDX receive complete
Copyright 2011 Texas Instruments Incorporated
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