TMS320TCI6602 Datasheet, PDF (185/201 Pages) Texas Instruments – Multicore Fixed and Floating-Point Digital Signal Processor

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7.16 UART Peripheral
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
The universal asynchronous receiver/transmitter (UART) module provides an interface between the DSP and
UART terminal interface or other UART-based peripheral. The UART is based on the industry standard TL16C550
asynchronous communications element, which in turn is a functional upgrade of the TL16C450. Functionally
similar to the TL16C450 on power up (single character or TL16C450 mode), the UART can be placed in an alternate
FIFO (TL16C550) mode. This relieves the DSP of excessive software overhead by buffering received and transmitted
characters. The receiver and transmitter FIFOs store up to 16 bytes including three additional bits of error status per
byte for the receiver FIFO.
The UART performs serial-to-parallel conversions on data received from a peripheral device and parallel-to-serial
conversion on data received from the DSP. The DSP can read the UART status at any time. The UART includes
control capability and a processor interrupt system that can be tailored to minimize software management of the
communications link. For more information on UART, see the Universal Asynchronous Receiver/Transmitter
(UART) for KeyStone Devices User Guide in 2.10 ‘‘Related Documentation from Texas Instruments’’ on page 63.
Table 7-71 UART Timing Requirements
(see Figure 7-47 and Figure 7-48)
No.
Parameter
4 tw(RXSTART)
5 tw(RXH)
5 tw(RXL)
6 tw(RXSTOP1)
6 tw(RXSTOP15)
6 tw(RXSTOP2)
8 td(CTSL-TX)
End of Table 7-71
Receive Timing
Pulse width, receive start bit
Pulse width, receive data/parity bit high
Pulse width, receive data/parity bit low
Pulse width, receive stop bit 1
Pulse width, receive stop bit 1.5
Pulse width, receive stop bit 2
Autoflow Timing Requirements
Delay time, CTS asserted to START bit transmit
1 P = CPU/6
Figure 7-47 UART Receive Timing Waveform
4
5
RXD
Stop/Idle
Start
Bit 0
Bit 1
Bit N-1 Bit N
5
Parity
Min
Max
Unit
0.96U
0.96U
0.96U
0.96U
0.96U
0.96U
P ⁽¹⁾
1.05U ns
1.05U ns
1.05U ns
1.05U ns
1.05U ns
1.05U ns
P ns
6
Stop
Idle
Start
Figure 7-48
UART CTS (Clear-to-Send Input) — Autoflow Timing Waveform
8
TXD
Bit N-1 Bit N
Stop
Start
Bit 0
CTS
Copyright 2011 Texas Instruments Incorporated
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