TMS320TCI6602 Datasheet, PDF (193/201 Pages) Texas Instruments – Multicore Fixed and Floating-Point Digital Signal Processor

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7.25 Serial RapidIO (SRIO) Port
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
The SRIO port on the TMS320TCI6602 device is a high-performance, low pin-count interconnect aimed for
embedded markets. The use of the RapidIO interconnect in a baseband board design can create a homogeneous
interconnect environment, providing even more connectivity and control among the components. RapidIO is based
on the memory and device addressing concepts of processor buses where the transaction processing is managed
completely by hardware. This enables the RapidIO interconnect to lower the system cost by providing lower latency,
reduced overhead of packet data processing, and higher system bandwidth, all of which are key for wireless
interfaces. For more information, see the Serial RapidIO (SRIO) for KeyStone Devices User Guide (literature number
SPRUGW1).
7.26 General-Purpose Input/Output (GPIO)
7.26.1 GPIO Device-Specific Information
On the TMS320TCI6602, the GPIO peripheral pins GP[15:0] are also used to latch configuration pins. For more
detailed information on device/peripheral configuration and the TCI6602 device pin muxing, see ‘‘Device
Configuration’’ on page 64. For more information on GPIO, see the General Purpose Input/Output (GPIO) for
KeyStone Devices User Guide (literature number SPRUGV1)
7.26.2 GPIO Electrical Data/Timing
Table 7-80 GPIO Input Timing Requirements
No.
1 t_w(GPOH)
2 t_w(GPOL)
End of Table 7-80
Pulse duration, GPOx high
Pulse duration, GPOx low
Min
Max Unit
12C
ns
12C
ns
Table 7-81 GPIO Output Switching Characteristics ⁽¹⁾
No.
1 t_w(GPOH)
2 t_w(GPOL)
End of Table 7-81
Parameter
Pulse duration, GPOx high
Pulse duration, GPOx low
1 Over recommended operating conditions.
Figure 7-57 GPIO Timing
1
2
GPIx
3
GPOx
Min
36C - 8
36C - 8
Max Unit
ns
ns
4
Copyright 2011 Texas Instruments Incorporated
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