TMS320TCI6602 Datasheet, PDF (155/201 Pages) Texas Instruments – Multicore Fixed and Floating-Point Digital Signal Processor

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Table 7-43
INTC0/INTC1 Register
Address Offset
0x498
0x49c
0x800
0x804
0x808
0x80c
0x810
0x814
0x818
0x81c
0x820
0x824
0x828
0x82c
0x830
0x834
0x838
0x83c
0x840
0x844
0x848
0x1500
0x1504
0x1508
End of Table 7-43
Register Mnemonic
CH_MAP_REG38
CH_MAP_REG39
HINT_MAP_REG0
HINT_MAP_REG1
HINT_MAP_REG2
HINT_MAP_REG3
HINT_MAP_REG4
HINT_MAP_REG5
HINT_MAP_REG6
HINT_MAP_REG7
HINT_MAP_REG8
HINT_MAP_REG9
HINT_MAP_REG10
HINT_MAP_REG11
HINT_MAP_REG12
HINT_MAP_REG13
HINT_MAP_REG14
HINT_MAP_REG15
HINT_MAP_REG16
HINT_MAP_REG17
HINT_MAP_REG18
ENABLE_HINT_REG0
ENABLE_HINT_REG1
ENABLE_HINT_REG2
TMS320TCI6602
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS782A—August 2011
Register Name
Interrupt Channel Map Register for 152 to 152+3
Interrupt Channel Map Register for 156 to 156+3
Host Interrupt Map Register for 0 to 0+3
Host Interrupt Map Register for 4 to 4+3
Host Interrupt Map Register for 8 to 8+3
Host Interrupt Map Register for 12 to 12+3
Host Interrupt Map Register for 16 to 16+3
Host Interrupt Map Register for 20 to 20+3
Host Interrupt Map Register for 24 to 24+3
Host Interrupt Map Register for 28 to 28+3
Host Interrupt Map Register for 32 to 32+3
Host Interrupt Map Register for 36 to 36+3
Host Interrupt Map Register for 40 to 40+3
Host Interrupt Map Register for 44 to 44+3
Host Interrupt Map Register for 48 to 48+3
Host Interrupt Map Register for 52 to 52+3
Host Interrupt Map Register for 56 to 56+3
Host Interrupt Map Register for 60 to 60+3
Host Interrupt Map Register for 64 to 64+3
Host Interrupt Map Register for 68 to 68+3
Host Interrupt Map Register for 72 to 72+3
Host Int Enable Register 0
Host Int Enable Register 1
Host Int Enable Register 2
7.10.2.2 INTC2 Register Map
Table 7-44 INTC2 Register
Address Offset
0x0
0x10
0x20
0x24
0x28
0x2c
0x34
0x38
0x200
0x204
0x208
0x20c
0x210
0x280
Register Mnemonic
REVISION_REG
GLOBAL_ENABLE_HINT_REG
STATUS_SET_INDEX_REG
STATUS_CLR_INDEX_REG
ENABLE_SET_INDEX_REG
ENABLE_CLR_INDEX_REG
HINT_ENABLE_SET_INDEX_REG
HINT_ENABLE_CLR_INDEX_REG
RAW_STATUS_REG0
RAW_STATUS_REG1
RAW_STATUS_REG2
RAW_STATUS_REG3
RAW_STATUS_REG4
ENA_STATUS_REG0
Register Name
Revision Register
Global Host Int Enable Register
Status Set Index Register
Status Clear Index Register
Enable Set Index Register
Enable Clear Index Register
Host Int Enable Set Index Register
Host Int Enable Clear Index Register
Raw Status Register 0
Raw Status Register 1
Raw Status Register 2
Raw Status Register 3
Raw Status Register 4
Enabled Status Register 0
Copyright 2011 Texas Instruments Incorporated
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