DMVA3 Datasheet, PDF (73/287 Pages) Texas Instruments – DMVA3 and DMVA4 DaVinc Digital Media Processor

DMVA3, DMVA4
www.ti.com
SPRS872B – MAY 2013 – REVISED DECEMBER 2013
3.3.8 EMAC [(R)(G)MII Modes] and MDIO
3.3.8.1 EMAC
Table 3-19. EMAC Terminal Functions [(R)(G)MII]
SIGNAL NAME [1]
EMAC[0]_GMTCLK/EMAC[1]_RGRXC
EMAC[0]_MCOL/EMAC[0]_RGRXCTL
EMAC[0]_MCRS/EMAC[0]_RGRXD[2]
EMAC[0]_MRCLK/EMAC[0]_RGTXC
EMAC[0]_MRXDV/EMAC[1]_RGRXD[1]
EMAC[0]_MRXD[0]/EMAC[0]_RGTXD[0]
EMAC[0]_MRXD[1]/EMAC[0]_RGRXD[0]
EMAC[0]_MRXD[2]/EMAC[0]_RGRXD[1]
EMAC[0]_MRXD[3]/EMAC[1]_RGRXCTL
EMAC[0]_MRXD[4]/EMAC[0]_RGRXD[3]
EMAC[0]_MRXD[5]/EMAC[0]_RGTXD[3]
EMAC[0]_MRXD[6]/EMAC[0]_RGTXD[2]
EMAC[0]_MRXD[7]/EMAC[0]_RGTXD[1]
EMAC[0]_MRXER/EMAC[0]_RGTXCTL
EMAC[0]_MTCLK/EMAC[0]_RGRXC
EMAC[0]_MTXD[0]/EMAC[1]_RGRXD[3]
EMAC[0]_MTXD[1]/EMAC[1]_RGTXD[1]
EMAC[0]_MTXD[2]/EMAC[1]_RGTXCTL
EMAC[0]_MTXD[3]/EMAC[1]_RGTXD[0]
EMAC[0]_MTXD[4]/EMAC[1]_RGTXD[2]
EMAC[0]_MTXD[5]/EMAC[1]_RGTXC
EMAC[0]_MTXD[6]/EMAC[1]_RGRXD[0]
EMAC[0]_MTXD[7]/EMAC[1]_RGTXD[3]
EMAC[0]_MTXEN/EMAC[1]_RGRXD[2]
EMAC[0]_RMCRSDV
EMAC[0]_RMRXD[0]
EMAC[0]_RMRXD[1]
EMAC[0]_RMRXER
EMAC[0]_RMTXD[0]
EMAC[0]_RMTXD[1]
EMAC[0]_RMTXEN
EMAC[1]_GMTCLK
EMAC[1]_MCOL
EMAC[1]_MCRS
EMAC[1]_MRCLK
EMAC[1]_MRXD[0]
EMAC[1]_MRXD[1]
EMAC[1]_MRXD[2]
EMAC[1]_MRXD[3]
EMAC[1]_MRXD[4]
EMAC[1]_MRXD[5]
EMAC[1]_MRXD[6]
DESCRIPTION [2]
TYPE [3] AAR BALL [4]
GMII Source Asynchronous Transmit Clock / RGMII
I/O
AL6
Receive Clock
[G]MII Collision Detect (Sense) input / RGMII Receive I
AH1
Control
[G]MII Carrier Sense input / RGMII Receive Data
I
AH2
[G]MII Receive Clock / RGMII Transmit Clock
I/O
AK1
[G]MII Receive Data Valid input / RGMII Receive Data I/O
AJ6
[G]MII Receive Data / RGMII Transmit Data
I/O
AK2
[G]MII Receive Data / RGMII Receive Data
I/O
AL2
[G]MII Receive Data / RGMII Receive Data
I/O
AL3
[G]MII Receive Data / RGMII Receive Control
I/O
AK3
[G]MII Receive Data / RGMII Receive Data
I/O
AK4
[G]MII Receive Data / RGMII Transmit Data
I/O
AJ4
[G]MII Receive Data / RGMII Transmit Data
I/O
AL5
[G]MII Receive Data / RGMII Transmit Data
I/O
AK5
[G]MII Receive Data Error input / RGMII Transmit Enable I/O
AJ2
[G]MII Transmit Clock input / RGMII Receive Clock
I/O
AG4
[G]MII Transmit Data / RGMII Receive Data
I/O
AK6
[G]MII Transmit Data / RGMII Transmit Data
I/O
AJ7
[G]MII Transmit Data / RGMII Trasmit Enable
I/O
AK7
[G]MII Transmit Data / RGMII Transmit Data
I/O
AE4
[G]MII Transmit Data / RGMII Transmit Data
I/O
AK8
[G]MII Transmit Data / RGMII Transmit Clock
I/O
AJ8
[G]MII Transmit Data / RGMII Receive Data
I/O
AH8
[G]MII Transmit Data / RGMII Transmit Data
I/O
AG8
[G]MII Transmit Data Enable output / RGMII Receive
I/O
AF8
Data
RMII Carrier Sense input
I
AK1
RMII Receive Data
I
AH1
RMII Receive Data
I
AH2
RMII Receive Data Error input
I
AJ2
RMII Transmit Data
O
AK2
RMII Transmit Data
O
AL2
RMII Transmit Data Enable output
O
AL3
GMII Source Asynchronous Transmit Clock
O
H4
[G]MII Collision Detect (Sense) input
I
E2
[G]MII Carrier Sense input
I
F5
[G]MII Receive Clock
I
F2
[G]MII Receive Data
I
F3
[G]MII Receive Data
I
G1
[G]MII Receive Data
I
G2
[G]MII Receive Data
I
H3
[G]MII Receive Data
I
G3
[G]MII Receive Data
I
H5
[G]MII Receive Data
I
H6
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