DMVA3 Datasheet, PDF (258/287 Pages) Texas Instruments – DMVA3 and DMVA4 DaVinc Digital Media Processor

DMVA3, DMVA4
SPRS872B – MAY 2013 – REVISED DECEMBER 2013
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Table 8-75. Switching Characteristics Over Recommended Operating Conditions for McASP⁽¹⁾
(see Figure 8-85)
NO.
9 t_c(AHCLKRX)
10 t_w(AHCLKRX)
PARAMETER
Cycle time, MCA[X]_AHCLKR/X
Pulse duration, MCA[X]_AHCLKR/X high or low
OPP100/OPP120/
Turbo
MIN
20 ⁽²⁾
MAX
0.5P -
2.5 ⁽³⁾
UNIT
ns
ns
11 t_c(ACLKRX)
12 t_w(ACLKRX)
Cycle time, MCA[X]_ACLKR/X
Pulse duration, MCA[X]_ACLKR/X high or low
20
ns
0.5P -
2.5 ⁽³⁾
ns
13 t_{d(ACLKRX-AFSRX)}
Delay time, MCA[X]_ACLKR/X transmit edge to
MCA[X]_AFSR/X output valid
Delay time, MCA[X]_ACLKR/X transmit edge to
MCA[X]_AFSR/X output valid with Pad Loopback
ACLKR/X int
ACLKR/X ext in
ACLKR/X ext out
-2
5
1
11.5 _ns
1
11.5
14 t_d(ACLKX-AXR)
Delay time, MCA[X]_ACLKX transmit edge to
MCA[X]_AXR output valid
Delay time, MCA[X]_ACLKX transmit edge to
MCA[X]_AXR output valid with Pad Loopback
ACLKX int
ACLKX ext in
ACLKX ext out
-2
5
1
11.5 _ns
1
11.5
15 t_{dis(ACLKX-AXR)}
Disable time, MCA[X]_ACLKX transmit edge to
MCA[X]_AXR output high impedance
Disable time, MCA[X]_ACLKX transmit edge to
MCA[X]_AXR output high impedance with Pad
Loopback
ACLKX int
ACLKX ext in
ACLKX ext out
-2
5
1
11.5
ns
1
11.5
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) 50 MHz
(3) P = AHCLKR/X period.
258 Peripheral Information and Timings
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