DMVA3 Datasheet, PDF (217/287 Pages) Texas Instruments – DMVA3 and DMVA4 DaVinc Digital Media Processor

DMVA3, DMVA4
www.ti.com
SPRS872B – MAY 2013 – REVISED DECEMBER 2013
8.13.1 ISS Peripheral Register Description
The ISS peripheral registers are described in the device-specific Technical Reference Manual. Each
register is documented as an offset from a base address for the peripheral. The base addresses for all of
the peripherals are in the device memory map (see Section 2.10).
8.13.2 ISSCAM Electrical Data/Timing
Table 8-44. Timing Requirements for ISSCAM⁽¹⁾ (see Figure 8-47)
N
O.
1 t_c(PCLK)
Cycle time, PCLK
2 t_w(PCLKH) Pulse duration, PCLK high
3 t_w(PCLKL) Pulse duration, PCLK low
4 t_t(PCLK)
Transition time, PCLK
t_su(DATA-
PCLK)
t_su(DE-PCLK)
5 t_su(VS-PCLK) Input setup time, Data/Control valid before PCLK high/low
t_su(HS-PCLK)
t_su(FLD-
PCLK)
t_h(PCLK-
DATA)
Input hold time, Data valid after PCLK high/low
6 ^th(PCLK-DE)
t_{h(PCLK-VS) Input hold time, Control valid after PCLK high/low}
t_h(PCLK-HS)
t_h(PCLK-FLD)
(1) H = period of baud rate, 1/programmed baud rate.
≤ 148.5 MHz clock rate
> 148.5 MHz and
≤ 162 MHz clock rate
OPP100/OPP120/Turb
o
UNIT
MIN NOM MAX
6.17
ns
2.78
ns
2.78
ns
2.64 ns
3.11
ns
3.11
ns
3.11
ns
3.11
ns
3.11
ns
-0.5
ns
0.0
ns
-0.5
ns
-0.5
ns
-0.5
ns
-0.5
ns
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Peripheral Information and Timings 217