DMVA3 Datasheet, PDF (116/287 Pages) Texas Instruments – DMVA3 and DMVA4 DaVinc Digital Media Processor

DMVA3, DMVA4
SPRS872B – MAY 2013 – REVISED DECEMBER 2013
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Table 4-9. Pins Used in EMAC[0] MII/GMII, RGMII, and RMII Boot Modes (continued)
PIN NO.
AK5
AJ6
AJ2
AG4
AK6
AJ7
AK7
AE4
AK8
AJ8
AH8
AG8
AF8
AG2
AG3
MII/GMII
EMAC[0]_MRXD[7]
EMAC[0]_MRXDV
EMAC[0]_MRXER
EMAC[0]_MTCLK
EMAC[0]_MTXD[0]
EMAC[0]_MTXD[1]
EMAC[0]_MTXD[2]
EMAC[0]_MTXD[3]
EMAC[0]_MTXD[4]
EMAC[0]_MTXD[5]
EMAC[0]_MTXD[6]
EMAC[0]_MTXD[7]
EMAC[0]_MTXEN
MDCLK
MDIO
TYPE
I
I
I
I
O
O
O
O
O
O
O
O
O
O
I/O
SIGNAL NAMES
RGMII
EMAC[0]_RGTXD[1]
DEFAULT
EMAC[0]_RGTXCTL
EMAC[0]_RGRXC
DEFAULT
DEFAULT
DEFAULT
DEFAULT
DEFAULT
DEFAULT
DEFAULT
DEFAULT
DEFAULT
MDCLK
MDIO
TYPE
O
O
I
O
I/O
RMII
DEFAULT
DEFAULT
EMAC[0]_RMRXER
DEFAULT
DEFAULT
DEFAULT
DEFAULT
DEFAULT
DEFAULT
DEFAULT
DEFAULT
DEFAULT
DEFAULT
MDCLK
MDIO
TYPE
I
O
I/O
4.2.7 PCIe Bootmode (PCIE_32 and PCIE_64)
Table 4-10 lists the device pins that are configured by the ROM for the PCIe boot mode.
Table 4-10. Pins Used in PCIe Bootmode
SIGNAL NAME
PCIE_TXP0
PCIE_TXN0
PCIE_RXP0
PCIE_RXN0
SERDES_CLKP
SERDES_CLKN
PIN NO.
L31
K31
K30
J30
H30
H31
TYPE
O
O
I
I
I
I
4.2.8 UART Bootmode
Table 4-11 lists the device pins that are configured by the ROM for the UART boot mode.
Table 4-11. Pins Used in UART Bootmode
SIGNAL NAME
UART0_RXD
UART0_TXD
PIN NO.
J26
E28
TYPE
I
O
4.3 Pin Multiplexing Control
Device level pin multiplexing is controlled on a pin-by-pin basis by the MUXMODE bits of the PINCNTL1 –
PINCNTL270 registers in the Control Module.
Pin multiplexing selects which one of several peripheral pin functions controls the pin's I/O buffer output
data values. Table 4-12 shows the peripheral pin functions associated with each MUXMODE setting for all
multiplexed pins. The default pin multiplexing control for almost every pin is to select MUXMODE = 0x0, in
which case the pin's I/O buffer is 3-stated.
116 Device Configurations
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