DMVA3 Datasheet, PDF (259/287 Pages) Texas Instruments – DMVA3 and DMVA4 DaVinc Digital Media Processor

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MCA[x]_ACLKR/X (Falling Edge Polarity)
MCA[x]_AHCLKR/X (Rising Edge Polarity)
MCA[x]_ACLKR/X (CLKRP = CLKXP = 1)^(A)
MCA[x]_ACLKR/X (CLKRP = CLKXP = 0)^(B)
MCA[x]_AFSR/X (Bit Width, 0 Bit Delay)
MCA[x]_AFSR/X (Bit Width, 1 Bit Delay)
MCA[x]_AFSR/X (Bit Width, 2 Bit Delay)
MCA[x]_AFSR/X (Slot Width, 0 Bit Delay)
MCA[x]_AFSR/X (Slot Width, 1 Bit Delay)
MCA[x]_AFSR/X (Slot Width, 2 Bit Delay)
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DMVA3, DMVA4
SPRS872B – MAY 2013 – REVISED DECEMBER 2013
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MCA[x]_AXR[x] (Data Out/Transmit)
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A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
C31
A. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
receiver is configured for rising edge (to shift data in).
B. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
receiver is configured for falling edge (to shift data in).
Figure 8-85. McASP Output Timing
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Peripheral Information and Timings 259