DS90UR903Q Datasheet, PDF (7/34 Pages) Texas Instruments – DS90UR903Q/DS90UR904Q 10 - 43MHz 18 Bit Color FPD-Link II Serializer and Deserializer

DS90UR904Q Deserializer Pin Descriptions
Pin Name
Pin No.
I/O, Type
LVCMOS PARALLEL INTERFACE
ROUT[20:0]
5, 6, 8, 9, 10,
11, 12, 13, 14,
15, 16, 18, 19,
21, 22, 23, 24,
25, 26, 27, 28
Outputs,
LVCMOS
PCLK
4
Output,
LVCMOS
Parallel data outputs.
Description
Pixel Clock Output Pin.
Strobe edge set by RRFB control register.
SERIAL CONTROL BUS - I²C COMPATIBLE
SCL
SDA
2
Input,
Clock line for the serial control bus communication
Open Drain SCL requires an external pull-up resistor to V_DDIO.
Input/Output, Data line for the serial control bus communication
1
Open Drain SDA requires an external pull-up resistor to V_DDIO.
I²C Mode select
MODE
47
Input, LVCMOS MODE = H -REQUIRED. The MODE pin must be set HIGH to allow I²C configuration
w/ pull up of the deserializer.
ID[x]
Device ID Address Select
48
Input, analog
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 4
CONTROL AND CONFIGURATION
Power down Mode Input Pin.
PDB
PDB = H, Deserializer is enabled and is ON.
35
Input, LVCMOS
w/ pull down ^{PDB = L, Deserializer is in Power Down mode. When the Deserializer is in Power}
Down. Programmed control register data are NOT retained and reset to default
values.
LOCK Status Output Pin.
LOCK
34
Output,
LVCMOS
LOCK = H, PLL is Locked, outputs are active
LOCK = L, PLL is unlocked, ROUT and PCLK output states are controlled by
OSS_SEL control register. May be used as Link Status.
Reserved.
RES
37, 38, 39, 43,
44, 46
-
Pin 46: This pin MUST be tied LOW.
Pin 37, 43, 44: Leave pin open.
Pins 38, 39: Route to test point or leave open if unused.
NC
30, 31, 32, 33
No Connect
FPD-LINK II INTERFACE
RIN+
41
RIN-
42
Input, CML
Inputt, CML
Noninverting differential input. The interconnect must be AC Coupled with a 100 nF
capacitor.
Inverting differential input. The interconnect must be AC Coupled with a 100 nF
capacitor.
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