DS90UR903Q Datasheet, PDF(15/34 Page) Texas Instruments – DS90UR903Q/DS90UR904Q 10 - 43MHz 18 Bit Color FPD-Link II Serializer and Deserializer

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DS90UR903Q Datasheet, PDF (15/34 Pages) Texas Instruments – DS90UR903Q/DS90UR904Q 10 - 43MHz 18 Bit Color FPD-Link II Serializer and Deserializer

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Symbol

CIN

VOL

Parameter

Input Pin Capacitance

Low Level Output Voltage

Conditions

SCL and SDA

VDDIO = 3.0V

IOL = 1.5mA

SCL and SDA

VDDIO = 1.71V

IOL = 1mA

Min

Typ

Max

Units

0.36

Note 1: âAbsolute Maximum Ratingsâ indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability

and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in

the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional; the device

should not be operated beyond such conditions.

Note 2: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified

or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.

Note 3: Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD, ÎVOD,

VTH and VTL which are differential voltages.

Note 4: Typical values represent most likely parametric norms at 1.8V or 3.3V, TA = +25Â°C, and at the Recommended Operation Conditions at the time of product

characterization and are not guaranteed.

Note 5: tPLD and tDDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK

Note 6: tDCJ is the maximum amount of jitter measured over 30,000 samples based on Time Interval Error (TIE).

Note 7: tDPJ is the maximum amount the period is allowed to deviate measured over 30,000 samples.

Note 8: tDCCJ is the maximum amount of jitter between adjacent clock cycles measured over 30,000 samples.

Note 9: Supply noise testing was done with minimum capacitors (as shown on Figures 27, 28) on the PCB. A sinusoidal signal is AC coupled to the VDDn (1.8V)

supply with amplitude = 25 mVp-p measured at the device VDDn pins. Bit error rate testing of input to the Ser and output of the Des with 10 meter cable shows

no error when the noise frequency on the Ser is less than 1 MHz. The Des on the other hand shows no error when the noise frequency is less than 750 kHz.

Note 10: Specification is guaranteed by characterization and is not tested in production.

Note 11: Specification is guaranteed by design.

Note 12: Recommended Input Timing Requirements are input specifications and not tested in production.

Note 13: UI â Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.

Note 14: tRJIT max (0.61UI) is limited by instrumentation and actual tRJIT of in-band jitter at low frequency (<2 MHz) is greater 1 UI.

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