DS90UR903Q Datasheet, PDF (5/34 Pages) Texas Instruments – DS90UR903Q/DS90UR904Q 10 - 43MHz 18 Bit Color FPD-Link II Serializer and Deserializer

DS90UR903Q Serializer Pin Descriptions
Pin Name
Pin No.
I/O, Type
Description
LVCMOS PARALLEL INTERFACE
DIN[20:0]
5, 4, 3, 2, 1, Inputs, LVCMOS Parallel data inputs.
40, 39, 38, 37, w/ pull down
36, 35, 33, 32,
30, 29, 28, 27,
26, 25, 24, 23
PCLK
6
Input, LVCMOS Pixel Clock Input Pin. Strobe edge set by TRFB control register.
w/ pull down
SERIAL CONTROL BUS - I²C COMPATIBLE
SCL
SDA
MODE
7
Input,
Clock line for the serial control bus communication
Open Drain SCL requires an external pull-up resistor to V_DDIO.
Input/Output, Data line for the serial control bus communication
8
Open Drain SDA requires an external pull-up resistor to V_DDIO.
I²C Mode select
Input, LVCMOS
12
MODE = H,- REQUIRED. The MODE pin must be set HIGH to allow I²C
w/ pull down
configuration of the serializer.
ID[x]
Device ID Address Select
9
Input, analog
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 3
CONTROL AND CONFIGURATION
PDB
Power down Mode Input Pin.
13
Input, LVCMOS
w/ pull down
PDB = H, Serializer is enabled and is ON.
PDB = L, Serailizer is in Power Down mode. When the Serializer is in Power Down,
the PLL is shutdown, and IDD is minimized. Programmed control register data are
NOT retained and reset to default values
RES
10, 11
Input, LVCMOS Reserved.
w/ pull down This pin MUST be tied LOW.
NC
22, 21, 20, 19
No Connect
FPD-LINK II INTERFACE
DOUT+
17
Output, CML Non-inverting differential output. The interconnect must be AC Coupled with a 100
nF capacitor.
DOUT-
16
Output, CML Inverting differential output. The interconnect must be AC Coupled with a 100 nF
capacitor.
POWER AND GROUND
VDDPLL
14
Power, Analog PLL Power, 1.8V ±5%
VDDT
15
Power, Analog Tx Analog Power, 1.8V ±5%
VDDCML
18
Power, Analog CML Power, 1.8V ±5%
VDDD
34
Power, Digital Digital Power, 1.8V ±5%
VDDIO
VSS
31
DAP
Power, Digital
Ground, DAP
Power for I/O stage. The single-ended inputs and SDA, SCL are powered from
V_DDIO. V_DDIO can be connected to a 1.8V ±5% or 3.3V ±10%
DAP must be grounded. DAP is the large metal contact at the bottom side, located
at the center of the LLP package. Connected to the ground plane (GND) with at
least 16 vias.
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