DS90UR903Q Datasheet, PDF (25/34 Pages) Texas Instruments – DS90UR903Q/DS90UR904Q 10 - 43MHz 18 Bit Color FPD-Link II Serializer and Deserializer

Functional Description
The DS90UR903Q/904Q FPD-Link II chipset is intended for
video display applications. The Serializer/ Deserializer
chipset operates from a 10 MHz to 43 MHz pixel clock fre-
quency. The DS90UR903Q transforms a 21-bit wide parallel
LVCMOS data bus into a single high-speed differential pair.
The high-speed serial bit stream contains an embedded clock
and DC-balance information which enhances signal quality to
support AC coupling. The DS90UR904Q receives the single
serial data stream and converts it back into a 21-bit wide par-
allel data bus.
DISPLAY APPLICATION
The DS90UR903Q/904Q chipset is intended for interface be-
tween a host (graphics processor) and a Display. It supports
a 21 bit parallel video bus for 18-bit color depth (RGB666)
display format. In a RGB666 configuration, 18 color bits (R
[5:0], G[5:0], B[5:0]), Pixel Clock (PCLK) and three control bits
(VS, HS and DE) are supported across the serial link.
The DS90UR903Q Serializer accepts a 21-bit parallel data
bus. The parallel data is converted into a single differential
link. The DS90UR904Q Deserializer extracts the clock/con-
trol information from the incoming data stream and recon-
structs the 21-bit parallel data.
FIGURE 21. Typical Display System Diagram
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CAMERA APPLICATION
Camera applications are also supported by the
DS90UR903Q/904Q chipset. The host controller/processsor
is connected to the deserializer, while the CMOS image sen-
sor provides data to the serializer.
FIGURE 22. Typical Camera System Diagram
SERIAL FRAME FORMAT
The DS90UR903Q/904Q chipset will transmit and receive a
pixel of data in the following format:
www.national.com
FIGURE 23. Serial Bitstream for 28-bit Symbol
24
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