DS90UR903Q Datasheet, PDF (23/34 Pages) Texas Instruments – DS90UR903Q/DS90UR904Q 10 - 43MHz 18 Bit Color FPD-Link II Serializer and Deserializer

TABLE 2. DS90UR904Q Control Registers
Addr
(Hex)
0
1
2
3
Name
I²C Device ID
Reset
RESERVED
Auto Clock
OSS Select
SSCG
RESERVED
VDDIO Control
VDDIO Mode
RESERVED
RESERVED
RESERVED
RRFB
Bits
Field
7:1 DEVICE ID
0 DES ID SEL
7:3 RESERVED
2 RESERVED
1 DIGITALRESET0
0 DIGITALRESET1
7:6 RESERVED
5 AUTO_CLOCK
4 OSS_SEL
3:0 SSCG
7:6 RESERVED
5
VDDIO
CONTROL
4 VDDIO MODE
3 RESERVED
2 RESERVED
1 RESERVED
0 RRFB
R/W Default
Description
RW 0xC0'h 7-bit address of Deserializer;
0x60h
(1100_000X) default
0: Device ID is from ID[x]
1: Register I²C Device ID overrides ID[x]
0x00'h Reserved
RW
0
Reserved
RW
0
1: Resets the device to default register values. Does not
self clear affect device I²C Bus or Device ID
RW
0
1: Digital Reset, retains all register values
self clear
00'b Reserved
RW
0
1: Output PCLK or Internal 25 MHz Oscillator clock
0: Only PCLK when valid PCLK present
Output Sleep State Select
RW
0
0: Outputs = TRI-STATE, when LOCK = L
1: Outputs = LOW , when LOCK = L
0000'b
SSCG Select
0000: Normal Operation, SSCG OFF (default)
0001: fmod (kHz) PCLK/2168, fdev ±0.50%
0010: fmod (kHz) PCLK/2168, fdev ±1.00%
0011: fmod (kHz) PCLK/2168, fdev ±1.50%
0100: fmod (kHz) PCLK/2168, fdev ±2.00%
0101: fmod (kHz) PCLK/1300, fdev ±0.50%
0110: fmod (kHz) PCLK/1300, fdev ±1.00%
0111: fmod (kHz) PCLK/1300, fdev ±1.50%
1000: fmod (kHz) PCLK/1300, fdev ±2.00%
1001: fmod (kHz) PCLK/868, fdev ±0.50%
1010: fmod (kHz) PCLK/868, fdev ±1.00%
1011: fmod (kHz) PCLK/868, fdev ±1.50%
1100: fmod (kHz) PCLK/868, fdev ±2.00%
1101: fmod (kHz) PCLK/650, fdev ±0.50%
1110: fmod (kHz) PCLK/650, fdev ±1.00%
1111: fmod (kHz) PCLK/650, fdev ±1.50%
11'b Reserved
Auto voltage control
RW
1
0: Disable
1: Enable (auto detect mode)
VDDIO voltage set
RW
0
0: 1.8V
1: 3.3V
RW
1
Reserved
RW
0
Reserved
0
Reserved
Pixel Clock Edge Select
0: Parallel Interface Data is strobed on the Falling Clock
RW
1
Edge
1: Parallel Interface Data is strobed on the Rising Clock
Edge.
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