DS90UB903Q Datasheet, PDF (7/41 Pages) Texas Instruments – 10 - 43MHz 18 Bit Color FPD-Link III Serializer and Deserializer with Bidirectional Control Channel

Pin Name
Pin No.
FPD-LINK III INTERFACE
RIN+
41
RIN-
42
CMLOUTP
38
CMLOUTN
39
POWER AND GROUND
VDDSSCG
3
VDDIO1/2/3
VDDD
VDDR
VDDCML
VDDPLL
29, 20, 7
17
36
40
45
VSS
DAP
I/O, Type
Description
Input/Output,
CML
Input/Output,
CML
Output, CML
Output, CML
Non-inverting differential input, bidirectional control channel output. The
interconnect must be AC Coupled with a 100 nF capacitor.
Inverting differential input, bidirectional control channel output. The interconnect
must be AC Coupled with a 100 nF capacitor.
Non-inverting CML Output
Monitor point for equalized differential signal. Test port is enabled via control
registers.
Inverting CML Output
Monitor point for equalized differential signal. Test port is enabled via control
registers.
Power, Digital
Power, Digital
Power, Digital
Power, Analog
Power, Analog
Power, Analog
Ground, DAP
SSCG Power, 1.8V ±5%
Power supply must be connected regardless if SSCG function is in operation.
LVCMOS I/O Buffer Power, The single-ended outputs and control input are powered
from V_DDIO. V_DDIO can be connected to a 1.8V ±5% or 3.3V ±10%
Digital Core Power, 1.8V ±5%
Rx Analog Power, 1.8V ±5%
Bidirectional Channel Driver Power, 1.8V ±5%
PLL Power, 1.8V ±5%
DAP must be grounded. DAP is the large metal contact at the bottom side, located
at the center of the LLP package. Connected to the ground plane (GND) with at
least 16 vias.
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