DS90UB903Q Datasheet, PDF (11/41 Pages) Texas Instruments – 10 - 43MHz 18 Bit Color FPD-Link III Serializer and Deserializer with Bidirectional Control Channel

Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
t_LHT
CML Low-to-High
R_L = 100Ω (Figure 6)
Transition Time
t_HLT
CML High-to-Low
R_L = 100Ω (Figure 6)
Transition Time
t_DIS
Data Input Setup to PCLK Serializer Data Inputs
2.0
t_DIH
Data Input Hold from PCLK ^{(Figure 10)}
2.0
t_PLD
Serializer PLL Lock Time R_L = 100Ω (Note 5, Note 11)
t_SD
Serializer Delay
R_T = 100Ω
PCLK = 10–43 MHz
6.386T
Register 0x03h b[0] (TRFB = 1)
+5
(Figure 12)
t_JIND
Serializer Output
Serializer output intrinsic deterministic
Deterministic Jitter
jitter . Measured (cycle-cycle) with
PRBS-7 test pattern
PCLK = 43 MHz
(Note 4, Note 13)
t_JINR
Serializer Output Random Serializer output intrinsic random jitter
Jitter
(cycle-cycle). Alternating-1,0 pattern.
PCLK = 43 MHz
(Note 4, Note 13)
t_JINT
Peak-to-peak Serializer Serializer output peak-to-peak jitter
Output Jitter
includes deterministic jitter, random
jitter, and jitter transfer from serializer
input. Measured (cycle-cycle) with
PRBS-7 test pattern.
PCLK = 43 MHz
(Note 4, Note 13)
λ_STXBW
Serializer Jitter Transfer
Function -3 dB Bandwidth
PCLK = 43 MHz
Default Registers
(Figure 18) (Note 4)
δ_STX
Serializer Jitter Transfer PCLK = 43 MHz
Function (Peaking)
Default Registers
(Figure 18 ) (Note 4)
δ_STXf
Serializer Jitter Transfer
Function (Peaking
Frequency)
PCLK = 43 MHz
Default Registers
(Figure 18) (Note 4)
Typ
150
150
1
6.386T
+ 12
0.13
0.04
0.396
1.90
0.944
500
Max
330
330
2
6.386T
+ 19.7
Units
ps
ps
ns
ns
ms
ns
UI
UI
UI
MHz
dB
kHz
11
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