DS90UB903Q Datasheet, PDF (6/41 Pages) Texas Instruments – 10 - 43MHz 18 Bit Color FPD-Link III Serializer and Deserializer with Bidirectional Control Channel

DS90UB904Q Deserializer Pin Descriptions
Pin Name
Pin No.
I/O, Type
Description
LVCMOS PARALLEL INTERFACE
ROUT[20:0]
5, 6, 8, 9, 10,
11, 12, 13, 14,
15, 16, 18, 19,
21, 22, 23, 24,
25, 26, 27, 28
Outputs,
LVCMOS
Parallel data outputs.
PCLK
4
Output,
LVCMOS
Pixel Clock Output Pin.
Strobe edge set by RRFB control register.
GENERAL PURPOSE INPUT (GPI)
GPI[3:0]
30, 31, 32, 33
Input, LVCMOS
General-purpose input pins can be used to control and respond to various
commands.
BIDIRECTIONAL CONTROL BUS - I²C COMPATIBLE
SCL
SDA
2
Input/Output, Clock line for the bidirectional control bus communication
Open Drain SCL requires an external pull-up resistor to V_DDIO.
1
Input/Output, Data line for bidirectional control bus communication
Open Drain SDA requires an external pull-up resistor to V_DDIO.
I²C Mode select
MODE
MODE = L, Master mode; Device generates and drives the SCL clock line, where
47
Input, LVCMOS required such as Read. Device is connected to slave peripheral on the bus.
w/ pull up MODE = H, Slave mode (default); Device accepts SCL clock input and attached to
an I²C controller master on the bus. Slave mode does not generate the SCL clock,
but uses the clock generated by the Master for the data transfers.
ID[x]
Device ID Address Select
48
Input, analog
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 4
CONTROL AND CONFIGURATION
Power down Mode Input Pin.
PDB
35
Input, LVCMOS ^{PDB = H, Deserializer is enabled and is ON.}
w/ pull down ^{PDB = L, Deserializer is in Power Down mode. When the Deserializer is in Power}
Down. Programmed control register data are NOT retained and reset to default
values.
LOCK Status Output Pin.
LOCK
Output,
LOCK = H, PLL is Locked, outputs are active
34
LVCMOS LOCK = L, PLL is unlocked, ROUT and PCLK output states are controlled by
OSS_SEL control register. May be used as Link Status.
Reserved.
RES
38, 39, 43, 46
Pins 38, 39: Route to test point or leave open if unused. See also FPD-LINK III
-
INTERFACE pin description section.
Pin 46: This pin MUST be tied LOW.
Pin 43: Leave pin open.
BIST MODE
BISTEN
BIST Enable Pin.
44
Input, LVCMOS
w/ pull down
BISTEN = H, BIST Mode is enabled.
BISTEN = L, BIST Mode is disabled.
PASS Output Pin for BIST mode.
PASS
37
Output,
PASS = H, ERROR FREE Transmission
LVCOMS PASS = L, one or more errors were detected in the received payload.
Leave Open if unused. Route to test point (pad) recommended.
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