DS90UB903Q Datasheet, PDF (32/41 Pages) Texas Instruments – 10 - 43MHz 18 Bit Color FPD-Link III Serializer and Deserializer with Bidirectional Control Channel

FIGURE 31. BIST Timing Diagram
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Step 3: Stop at SPEED BIST by turning off BIST mode in the
Deserializer to determine Pass/Fail.
To end BIST, the system must pull BISTEN pin of the Dese-
rializer LOW. The BIST duration is fully defined by the BIS-
TEN width and Deserializer LOCK is HIGH; thus the Bit Error
Rate is determined by how long the system holds BISTEN
HIGH.
FIGURE 32. BIST BER Calculation
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Step 4: Place system in Normal Operating Mode by disabling
BIST at the Serializer.
Once Step 3 is complete, AT SPEED BIST is over and the
Deserializer is out of BIST mode. To fully return to Normal
mode, apply Normal input data into the Serializer.
Any PASS result will remain unless it is changed by a new
BIST session or cleared by asserting and releasing PDB. The
default state of PASS after a PDB toggle is HIGH.
It is important to note that AT SPEED BIST will only determine
if there is an issue on the link that is not related to the clock
and data recovery of the link (whose status is flagged with
LOCK pin).
LVCMOS VDDIO OPTION
1.8V or 3.3V SER Inputs and DES Outputs are user seletable
to provide compatibility with 1.8V and 3.3V system interfaces.
REMOTE WAKE UP (Camera Mode)
After initial power up, the Serializer is in a low-power Standby
mode. The Deserializer (controlled by ECU/MCU) 'Remote
Wake-up' register allows the Deserializer side to generate a
signal across the link to remotely wake-up the Serializer.
Once the Serializer detects the wake-up signal Serializer
switches from Standby mode to active mode. In active mode,
the Serializer locks onto PCLK input (if present), otherwise
the on-chip oscillator is used as the input clock source. Note
the MCU controller should monitor the Deserializer LOCK pin
and confirm LOCK = H before performing any I²C communi-
cation across the link.
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