DS90UB903Q Datasheet, PDF (14/41 Pages) Texas Instruments – 10 - 43MHz 18 Bit Color FPD-Link III Serializer and Deserializer with Bidirectional Control Channel

FIGURE 4. Bidirectional Control Bus Timing
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Bidirectional Control Bus DC Characteristics (SCL, SDA) - I²C Compliant
Over recommended supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V_IH
Input High Level
SDA and SCL
V_IL
Input Low Level Voltage SDA and SCL
V_HY
Input Hysteresis
SDA and SCL
I_OZ
TRI-STATE Output Current PDB = 0V
V_OUT = 0V or V_DD
I_IN
Input Current
SDA or SCL,
Vin = V_DDIO or GND
C_IN
Input Pin Capacitance
V_OL
Low Level Output Voltage SCL and SDA
V_DDIO = 3.0V
I_OL = 1.5 mA
SCL and SDA
V_DDIO = 1.71V
I_OL = 1 mA
0.7 x
V_DDIO
V_DDIO
V
GND
0.3 x
V_DDIO
V
>50
mV
-20
±1
+20
µA
-20
±1
+20
µA
<5
pF
0.36
V
0.36
V
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional; the device
should not be operated beyond such conditions.
Note 2: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 3: Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD, ΔVOD,
VTH and VTL which are differential voltages.
Note 4: Typical values represent most likely parametric norms at 1.8V or 3.3V, T_A = +25°C, and at the Recommended Operation Conditions at the time of product
characterization and are not guaranteed.
Note 5: t_PLD and t_DDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK
Note 6: t_DCJ is the maximum amount of jitter measured over 30,000 samples based on Time Interval Error (TIE).
Note 7: t_DPJ is the maximum amount the period is allowed to deviate measured over 30,000 samples.
Note 8: t_DCCJ is the maximum amount of jitter between adjacent clock cycles measured over 30,000 samples.
Note 9: Supply noise testing was done with minimum capacitors (as shown on Figures 35, 36) on the PCB. A sinusoidal signal is AC coupled to the VDDn (1.8V)
supply with amplitude = 25 mVp-p measured at the device VDDn pins. Bit error rate testing of input to the Ser and output of the Des with 10 meter cable shows
no error when the noise frequency on the Ser is less than 1 MHz. The Des on the other hand shows no error when the noise frequency is less than 750 kHz.
Note 10: Specification is guaranteed by characterization and is not tested in production.
Note 11: Specification is guaranteed by design.
Note 12: Recommended Input Timing Requirements are input specifications and not tested in production.
Note 13: UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.
Note 14: t_RJIT max (0.61UI) is limited by instrumentation and actual t_RJIT of in-band jitter at low frequency (<2 MHz) is greater 1 UI.
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