CD4051B-Q1_15 Datasheet, PDF (7/24 Pages) Texas Instruments – CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS

CD4051B-Q1, CD4052B-Q1, CD4053B-Q1
CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS
WITH LOGIC−LEVEL CONVERSION
SCHS354A − AUGUST 2004 − REVISED JANUARY 2008
electrical characteristics, V_SUPPLY = ±5 V, A_V = 1 V, R_L = 100 Ω, unless otherwise noted
(see Note 2) (continued)
PARAMETER
TEST CONDITIONS
LIMITS AT INDICATED
V_EE V_DD
TEMPERATURES
(V) (V)
25°C
−40°C 125°C
MIN TYP
Control (Address or Inhibit), V_C
V_IL Input low voltage
V_IL = V_DD through 1kΩ,
V_IH = V_DD through 1kΩ,
R_L = 1kΩ to V_SS,
I_is < 2 µA on all OFF channels
V_IH Input high voltage
V_IL = V_DD through 1kΩ,
V_IH = V_DD through 1kΩ,
R_L = 1kΩ to V_SS,
I_is < 2 µA on all OFF channels
I_IN Input current
V_IN = 0 V, 18 V
Address-to-signal
t_r, t_f = 20 ns, C_L = 50 pF,
t_pd1
OUT (channels ON R_L = 10 kΩ, V_SS = 0 V,
or OFF) propagation See Figure 10, Figure 11, and
delay
Figure 14
V_SS
5
V_SS
10
V_SS
15
V_SS
5
V_SS
10
V_SS
15
18
0
5
0
10
0
15
−5
5
1.5
3
4
3.5
7
11
±0.1
1.5
3
4
3.5 3.5
7
7
11
11
±1
±10^−5
450
160
120
225
0
5
400
Inhibit-to-signal
t_pd2
OUT (channel
turning ON)
propagation delay
t_r, t_f = 20 ns, C_L = 50 pF,
R_L = 1 kΩ, V_SS = 0 V,
See Figure 11
0
10
0
15
−10
5
160
120
200
0
5
200
Inhibit-to-signal
OUT (channel
t_{pd3 turning OFF)}
propagation delay
t_r, t_f = 20 ns, C_L = 50 pF,
R_L = 10 kΩ, V_SS = 0 V,
See Figure 15
0
10
0
15
−10
5
90
70
130
Input capacitance,
C_IN any address or
5
inhibit input
NOTES: 2: Peak-to-peak voltage symmetrical about V_DD − V_EE
2
3: Determined by minimum feasible leakage measurement for automatic testing
MAX
1.5
3
4
±0.1
720
320
240
450
720
320
240
400
450
210
160
300
7.5
UNIT
V
V
µA
ns
ns
ns
pF
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