CD4051B-Q1_15 Datasheet, PDF (6/24 Pages) Texas Instruments – CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS

CD4051B-Q1, CD4052B-Q1, CD4053B-Q1
CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS
WITH LOGIC−LEVEL CONVERSION
SCHS354A − AUGUST 2004 − REVISED JANUARY 2008
recommended operating conditions
V_DD
Supply voltage
T_A
Operating free-air temperature
MIN MAX UNIT
5
20 V
−40 125 °C
electrical characteristics, V_SUPPLY = ±5 V, A_V = 1 V, R_L = 100 Ω, unless otherwise noted
(see Note 2)
PARAMETER
TEST CONDITIONS
LIMITS AT INDICATED
V_DD
TEMPERATURES
(V)
25°C
−40°C 125°C
MIN TYP
5
5 150
0.04
Quiescent device
I_DD
current
10
10 300
0.04
15
20 600
0.04
20
100 3000
0.08
Signal Input (V_is) and Output (V_os)
r_on
Drain-to-source
V_EE = 0 V, V_SS = 0 V,
ON-state resistance V_IS = 0 to V_DD
5
850 1300
470
10
330 550
180
15
210 320
125
ON-state resistance
5
15
∆r_on difference between V_EE = 0 V, V_SS = 0 V
10
10
any two switches
15
5
Input/output leakage
current (switch off)
Any channel OFF (MAX) or all channels
OFF (COM OUT/IN) (Max),
V_EE = 0 V, V_SS = 0 V, See Note 3
C_is
Input capacitance
V_EE = −5 V, V_SS = −5 V
CD4051
18
±0.1
±1
5
±10^−5
5
30
C_os Output capacitance V_EE = −5 V, V_SS = −5 V CD4052
5
18
CD4053
9
C_ios
Feedthrough
capacitance
V_EE = −5 V, V_SS = −5 V
5
0.2
t_pd
Propagation delay
(signal input to
output)
V_IS(p-p) = V_DD, R_L = 200 kΩ,
C_L = 50 pF, t_r, t_f = 20 ns
5
10
15
30
15
10
NOTES: 2. Peak-to-peak voltage symmetrical about V_DD − V_EE
2
3. Determined by minimum feasible leakage measurement for automatic testing
MAX
5
10
20
100
1050
400
240
±0.1
60
30
20
UNIT
µA
Ω
Ω
µA
pF
pF
pF
ns
6
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