CD4051B-Q1_15 Datasheet, PDF (1/24 Pages) Texas Instruments – CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS

CD4051B-Q1, CD4052B-Q1, CD4053B-Q1
CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS
WITH LOGIC−LEVEL CONVERSION
SCHS354A − AUGUST 2004 − REVISED JANUARY 2008
Features
D Qualified for Automotive Applications
D Wide Range of Digital and Analog Signal
Levels
− Digital: 3 V to 20 V
− Analog: 3 20 V_P-P
D Low ON Resistance, 125 Ω (Typ) Over
15 V_P-P Signal Input Range
for V_DD − V_EE = 18 V
D High OFF Resistance, Channel Leakage of
+100 pA (Typ) at V_DD − V_EE = 18 V
D Logic-Level Conversion for Digital
Addressing Signals of 3 V to 20 V
(V_DD − V_SS = 3 V to 20 V) to Switch Analog
Signals to 20 V_P-P (V_DD − V_EE = 20 V)
D Matched Switching Characteristics,
r_on = 5 Ω (Typ) for V_DD − V_EE = 15 V
D Very Low Quiescent Power Dissipation
Under All Digital-Control Input and Supply
Conditions, 0.2 µW (Typ)
at V_DD − V_SS = V_DD − V_EE = 10 V
D Binary Address Decoding on Chip
D 5-V, 10-V, and 15-V Parametric Ratings
D 100% Tested for Quiescent Current at 20 V
D Maximum Input Current of 1µA at 18 V Over
Full Package Temperature Range, 100 nA at
18 V and 25°C
D Break-Before-Make Switching Eliminates
Channel Overlap
Applications
D Analog and Digital Multiplexing and
Demultiplexing
D Analog-to-Digital (A/D) and
Digital-to-Analog (D/A) Conversion
D Signal Gating
description/ordering information
The CD4051B, CD4052B, and CD4053B analog multiplexers are digitally-controlled analog switches that have
low ON impedance and very low OFF leakage current. Control of analog signals up to 20 V_P-P can be achieved
by digital signal amplitudes of 4.5 V to 20 V (If V_DD − V_SS = 3 V, a V_DD − V_EE of up to 13 V can be controlled;
for V_DD − V_EE level differences above 13 V, a V_DD − V_SS of at least 4.5 V is required). For example, if
V_DD = 4.5 V, V_SS = 0 V, and V_EE = −13.5 V, analog signals from −13.5 V to 4.5 V can be controlled by digital
inputs of 0 V to 5 V. These multiplexer circuits dissipate extremely low quiescent power over the full V_DD − V_SS
and V_DD − V_EE supply-voltage ranges, independent of the logic state of the control signals. When a logic high
(H) is present at the inhibit (INH) input, all channels are off.
ORDERING INFORMATION^†
T_A
PACKAGE^‡
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SOIC − M
Reel of 2500 CD4051BQM96Q1
CD4051Q
−40°C to 125°C
TSSOP − PW
SOIC − M
TSSOP − PW
Reel of 2000
Reel of 2500
Reel of 2000
CD4051BQPWRQ1
CD4052BQM96Q1^§
CD4052BQPWRQ1^§
CM051BQ
CD4052Q
CD4052Q
SOIC − M
Reel of 2500 CD4053BQM96Q1
CD4053Q
TSSOP − PW
Reel of 2000 CD4053BQPWRQ1^§
CD4053Q
† _{For the most current package and ordering information, see the Package Option Addendum at the end of this}
document, or see the TI web site at http://www.ti.com.
‡ _{Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.}
§ _{Product Preview}
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UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
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