CD4051B-Q1_15 Datasheet, PDF (12/24 Pages) Texas Instruments – CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS

CD4051B-Q1, CD4052B-Q1, CD4053B-Q1
CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS
WITH LOGIC−LEVEL CONVERSION
SCHS354A − AUGUST 2004 − REVISED JANUARY 2008
PARAMETER MEASUREMENT INFORMATION
V_DD
V_DD
V_DD
1
16
2
15
3
14 IDD
4
13
5
12
6
11
7
10
8
9
CD4051
1
16
2
15
3
14
I_DD
4
13
5
12
6
11
7
10
8 ^CD40529
CD4052
1
16
2
15
3
14
4
13
I_DD
5
12
6
11
7
10
8
9
CD4053
Figure 12. OFF Channel Leakage Current, Any Channel OFF
V_DD
V_DD
V_DD
1
16
2
15
I_DD
3
14
4
13
5
12
6
11
7
10
8
9
1
16
2
15
I_DD
3
14
4
13
5
12
6
11
7
10
8
9
1
16
2
15
I_DD
3
14
4
13
5
12
6
11
7
10
8
9
CD4051
CD4052
CD4053
Figure 13. OFF Channel Leakage Current, All Channels OFF
V_DD
Output
1
16
2
15
R_L
C_L
V_DD
3
14
4
13
V_EE
5
V_EE
6
7
8
12
V_DD
11
10
V_{SS Clock}
9
In
V_SS
CD4051 ^VSS
Output
1
2
C_L
R_L
3
V_{DD 4}
16
V_DD
15
14
13
V_{EE VEE}
V_SS
5
12
6
11
V_EE
7
10 ^VDD
8
9 ^{VSS Clock}
In
V_SS
CD4052 ^VSS
V_DD
1
16
Output
2
15
3
14
R_L
C_L
4
13
5
12
V_EE
6
11
V_DD
7
10
V_{SS Clock}
8
9
In
CD4053 _VSS
Figure 14. Propagation Delay, Address Input to Signal Output
Output
R_L
50 pF
V_DD
V_SS
V_EE
V_DD
Clock VEE
In _VSS
V_DD
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
t_PHL and t_PLH ^VSS
CD4051
Output
R_L
50 pF
V_DD
V_SS
Clock
In
V_EE
V_DD
V_EE
V_SS
V_DD
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
t_PHL and t_PLH ^VSS
CD4052
Output
R_L
50 pF
V_DD
V_{SS Clock}
In
V_EE
V_DD
V_EE
V_SS
Figure 15. Propagation Delay, Inhibit Input to Signal Output
1
16
V_DD
2
15
3
14
4
13
5
12
6
11
7
10
8
9
t_PHL and t_PLH VSS
CD4053
12
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