BQ29312_15 Datasheet, PDF (7/39 Pages) Texas Instruments – FOUR CELL LITHIUM-ION

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BAT
DSG
VC1
VC2
VC3
VC4
VC5
SR1
SR2
WDI
CELL
GND
PIN ASSIGNMENTS
PW PACKAGE
(TOP VIEW)
bq29312
SLUS546E – MARCH 2003 – REVISED MARCH 2005
1
24
OD
2
23
PMS
3
22
PACK
4
21
ZVCHG
5
20
CHG
6
19
SLEEP
7
18
REG
8
17
TOUT
9
16
XALERT
10
15
GND
11
14
SDATA
12
13
SCLK
TERMINAL
NAME
NO.
BAT
1
DSG
2
VC1
3
VC2
4
VC3
5
VC4
6
VC5
7
SR1
8
SR2
9
WDI
10
CELL
11
GND
12
SCLK
13
SDATA
14
GND
15
XALERT
16
TOUT
17
REG
18
SLEEP
19
CHG
20
ZVCHG
21
PACK
22
PMS
23
OD
24
Terminal Functions
DESCRIPTION
Diode protected BAT+ terminal and primary power source.
Push-pull output discharge FET gate drive
Sense voltage input terminal for most positive cell and balance current input for most positive cell.
Sense voltage input terminal for second most positive cell, balance current input for second most positive cell and
return balance current for most positive cell.
Sense voltage input terminal for third most positive cell, balance current input for third most positive cell and return
balance current for second most positive cell.
Sense voltage input terminal for least positive cell, balance current input for least positive cell and return balance
current for third most positive cell.
Sense voltage input terminal for most negative cell, return balance current for least positive cell.
Current sense positive terminal when charging relative to SR2
Current sense negative terminal when discharging relative to SR2 current sense terminal
Digital input that provides the timing clock for the OC and SC delays and also acts as the watchdog clock.
Output of scaled value of the measured cell voltage.
Analog ground pin and negative pack terminal
Open-drain bidirectional serial interface clock with internal 10 kΩ pull-up to V_(REG).
Open-drain bidirectional serial interface data with internal 10 kΩ pull-up to V_(REG).
Connect to GND
Open-drain output used to indicate status register changes. With internal 100 kΩ pull-up to V_(REG)
Provides thermistor bias current
Integrated 3.3-V regulator output
This pin is pulled up to V_(REG) internally, open or H level makes Sleep mode
Push-pull output charge FET gate drive
The ZVCHG FET drive is connected here
PACK positive terminal and alternative power source
0-V charge configuration select pin, CHG terminal ON/OFF is determined by this pin.
NCH FET open drain output
7