BQ29312_15 Datasheet, PDF (18/39 Pages) Texas Instruments – FOUR CELL LITHIUM-ION

bq29312
SLUS546E – MARCH 2003 – REVISED MARCH 2005
OUTPUT CTL: Output Control Register
OUTPUT CTL REGISTER (0x01)
7
6
5
4
3
0
0
0
OD
XZVCHG
2
CHG
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1
DSG
0
LTCLR
The OUTPUT CTL register controls the outputs of the bq29312 and can be used to clear certain states.
OUTPUT CTL b0 (LTCLR): When a current limit fault or watchdog timer fault is latched, this bit releases the fault
latch when toggled from 0 to 1 and back to 0 (default =0).
0 = (default)
0->1 ->0 clears the fault latches
OUTPUT CTL b1 (DSG): This bit controls the external discharge FET.
0 = discharge FET is off and is controlled by the system host (default).
1 = discharge FET is on and the bq29312 is in normal operating mode.
OUTPUT CTL b2 (CHG): This bit controls the external charge FET.
PMS=GND
0 = charge FET is off and is controlled by the system host (default).
1 = charge FET is on and the bq29312 is in normal operating mode.
PMS=PACK
0 = charge FET is off and is controlled by the system host.
1 = charge FET is on and the bq29312 is in normal operating mode (default).
OUTPUT CTL b3 (XZVCHG): This bit controls the external ZVCHG FET.
0 = ZVCHG FET is on and is controlled by the system host (default).
1 = ZVCHG FET is off and the bq29312 is in normal operating mode.
OUTPUT CTL b4 (OD): This bit enables or disables the OD output.
0 = OD is high impedance (default).
1 = OD output is active (GND).
STATE CTL: State Control Register
STATE CTL REGISTER (0x02)
7
6
5
4
3
0
0
0
0
0
2
WDDIS
1
SHIP
0
SLEEP
The STATE CTL register controls the state of the bq29312.
STATE CTL b0 (SLEEP): This bit is used to enter the sleep power mode.
0 = bq29312 exits sleep mode (default).
1 = bq29312 enters the sleep mode.
STATE CTL b1 (SHIP): This bit is used to enter the ship power mode when pack supply voltage is not applied.
0 = bq29312 in normal mode (default).
1 = bq29312 enters ship mode when pack voltage is removed.
STATE CTL b2 (WDDIS): This bit is used to enable or disable the watchdog timer function.
0 = enable clock monitoring (default).
1 = disable clock monitoring.
NOTE: Use caution when setting the WDDIS. For example, when the 32-kHz input fails, the overload and
short-circuit delay timers no longer function because they use the same WDI input. If the WDI input clock stops,
these current protections do not function. WDF should be enabled at any time for maximum safety. If the
watchdog function is disabled, the CHG and DSG FETs should be turned off.
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