BQ24070_14 Datasheet, PDF (7/33 Pages) Texas Instruments – System Power-Path Management IC

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bq24070, bq24071
SLUS694G – MARCH 2006 – REVISED DECEMBER 2014
Electrical Characteristics (continued)
over junction temperature range (0°C ≤ T_J ≤ 125°C) and the recommended supply voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
BATTERY RECHARGE THRESHOLD
V_RCH
Recharge threshold voltage
V_O(BAT-
REG)
–0.075
V_O(BAT-REG)
–0.100
V_O(BAT-REG)
–0.125
V
T_DGL(RCH)
Deglitch time for recharge
detection ⁽⁴⁾
R_(TMR) = 50 kΩ, V_I(BAT) increasing
or decreasing below threshold,
100-ns fall time, 10-mv overdrive
22.5
ms
STAT1, STAT2, AND PG, OPEN-DRAIN (OD) OUTPUTS⁽⁸⁾
V_OL
Low-level output saturation voltage
I_OL = 5 mA, An external pullup
resistor ≥ 1 K required.
0.25
V
I_LKG
Input leakage current
ISET2, CE INPUTS
1
5
μA
V_IL
V_IH
I_IL
I_IH
I_IL
I_IH
t_(CE-HLDOFF)
MODE INPUT
Low-level input voltage
High-level input voltage
Low-level input current, CE
High-level input current, CE
Low-level input current, ISET2
High-level input current, ISET2
Holdoff time, CE
V_ISET2 = 0.4 V
V_ISET2 = V_CC
CE going low only
0
0.4
V
1.4
–1
1
μA
–20
40
3.3
6.2
ms
V_IL
Low-level input voltage
Falling Hi→Low; 280 K ± 10% applied when
low.
0.975
1
1.025
V
V_IH
I_IL
TIMERS
High-level input voltage
Low-level input current, Mode
Input R_Mode sets external hysteresis
V_IL + .01
–1
V_IL + .024
V
μA
K_(TMR)
R_(TMR) ⁽⁹⁾
t_(PRECHG)
I_(FAULT)
Timer set factor
External resistor limits
Precharge timer
Timer fault recovery pullup from
OUT to BAT
t_(CHG) = K_(TMR) × R_(TMR)
0.313
0.360
0.414
s/Ω
30
100
kΩ
0.09 ×
t_(CHG)
0.10 × t_(CHG) 0.11 × t_(CHG)
s
1
kΩ
CHARGER SLEEP THRESHOLDS (PG THRESHOLDS, LOW → POWER GOOD)
V_(SLPENT) ⁽¹⁰⁾
V_(SLPEXIT) ⁽¹⁰⁾
Sleep-mode entry threshold
Sleep-mode exit threshold
V_(UVLO) ≤ V_I(BAT) ≤ V_O(BAT-REG),
No t_(BOOT-UP) delay
V_(UVLO) ≤ V_I(BAT) ≤ V_O(BAT-REG),
No t_(BOOT-UP) delay
V_VCC ≥
V_I(BAT)
+190 mV
V_VCC ≤
V_I(BAT)
+125 mV
V
t_(DEGL)
Deglitch time for sleep mode⁽¹¹⁾
R_(TMR) = 50 kΩ,
V_(IN) decreasing below threshold, 100-ns fall
time, 10-mv overdrive
22.5
ms
START-UP CONTROL BOOT-UP
t_(BOOT-UP)
Boot-up time
On the first application of input with Mode
Low
120
150
180
ms
(8) See Charger Sleep mode for PG (V_CC = V_IN) specifications.
(9) To disable the fast-charge safety timer and charge termination, tie TMR to the V_REF pin. Tying the TMR pin high changes the timing
resistor from the external value to an internal 50 kΩ ±25%, which can add an additional tolerance to any timed specification. The TMR
pin normally regulates to 2.5 V when the charge current is not restricted by the DPPM or thermal feedback loops. If these loops become
active, the TMR pin voltage will be reduced proportionally to the reduction in charge current and the clock frequency will be reduced by
the same percentage (timed durations will count down slower, extending their time). The TMR pin is clamped at 0.80 V, for a maximum
time extension of 2.5 V ÷ 0.8 V × 100 = 310%.
(10) The IC is considered in sleep mode when IN is absent (PG = OPEN DRAIN).
(11) Does not declare sleep mode until after the deglitch time and implement the needed power transfer immediately according to the
switching specification.
Copyright © 2006–2014, Texas Instruments Incorporated
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