TMS320F28075 Datasheet, PDF (63/182 Pages) Texas Instruments – Microcontrollers

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TMS320F28075
SPRS902B – OCTOBER 2014 – REVISED OCTOBER 2015
5.7.8.3 Low-Power Mode Wakeup Timing
Table 5-29 shows the IDLE mode timing requirements, Table 5-30 shows the switching characteristics,
and Figure 5-16 shows the timing diagram for IDLE mode.
Table 5-29. IDLE Mode Timing Requirements⁽¹⁾
t_w(WAKE)
Pulse duration, external wakeup signal
Without input qualifier
With input qualifier
(1) For an explanation of the input qualifier parameters, see Table 5-24.
MIN
2t_c(SYSCLK)
2t_c(SYSCLK) + t_w(IQSW)
MAX UNIT
cycles
Table 5-30. IDLE Mode Switching Characteristics⁽¹⁾
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
Delay time, external wake signal to program execution resume ⁽²⁾
MAX UNIT
t_d(WAKE-IDLE)
• Wakeup from Flash
– Flash module in active state
• Wakeup from Flash
– Flash module in sleep state
• Wakeup from RAM
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
40t_c(SYSCLK)
40t_c(SYSCLK) + t_w(WAKE)
6700t_c(SYSCLK) ⁽³⁾
6700t_c(SYSCLK) ⁽³⁾ + t_w(WAKE)
25t_c(SYSCLK)
25t_c(SYSCLK) + t_w(WAKE)
cycles
(1) For an explanation of the input qualifier parameters, see Table 5-24.
(2) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered
by the wakeup) signal involves additional latency.
(3) This value is based on the Flash power-up time, which is a function of the SYSCLK frequency, Flash Waitstates (RWAIT), and
FPAC1[PSLEEP]. For more information, see the "Flash and OTP Power-Down Modes and Wakeup" section of the TMS320F2807x
Piccolo Microcontrollers Technical Reference Manual (SPRUHM9). This value can be realized when SYSCLK is 120 MHz, RWAIT is 2,
and FPAC1[PSLEEP] is 0x860.
Address/Data
(internal)
t_d(WAKE-IDLE)
XCLKOUT
(A)
WAKE
t_w(WAKE)
A. WAKE can be any enabled interrupt, WDINT or XRS. After the IDLE instruction is executed, a delay of five OSCCLK
cycles (minimum) is needed before the wakeup signal could be asserted.
Figure 5-16. IDLE Entry and Exit Timing Diagram
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Specifications
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