TMS320F28075 Datasheet, PDF (31/182 Pages) Texas Instruments – Microcontrollers

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TMS320F28075
SPRS902B – OCTOBER 2014 – REVISED OCTOBER 2015
GPIO Index
GPyGMUXn.
GPIOz =
GPyMUXn.
GPIOz =
Table 4-4. GPIO Muxed Pins⁽¹⁾⁽²⁾ (continued)
GPIO Mux Selection
0, 4, 8, 12
1
2
3
5
6
00b, 01b,
10b, 11b
00b
01b
00b
01b
10b
11b
01b
10b
GPIO40
GPIO41
GPIO42
GPIO43
GPIO44
GPIO45
GPIO46
GPIO47
GPIO48
GPIO49
GPIO50
GPIO51
GPIO52
GPIO53
GPIO54
GPIO55
GPIO56
GPIO57
GPIO58
GPIO59
GPIO60
GPIO61
GPIO62
GPIO63
GPIO64
GPIO65
GPIO66
GPIO67
GPIO68
GPIO69
GPIO70
GPIO71
GPIO72
GPIO73
GPIO74
GPIO75
GPIO76
GPIO77
GPIO78
GPIO79
GPIO80
GPIO81
GPIO82
GPIO83
GPIO84
GPIO85
GPIO86
GPIO87
GPIO88
GPIO89
EM1A2 (O)
EM1A3 (O)
OUTPUTXBAR3 (O)
OUTPUTXBAR4 (O)
EQEP1A (I)
EQEP1B (I)
EQEP1S (I/O)
EQEP1I (I/O)
SPISIMOA (I/O)
SPISOMIA (I/O)
SPICLKA (I/O)
SPISTEA (I/O)
MCLKRA (I/O)
MFSRA (I/O)
MCLKRB (I/O)
MFSRB (I/O)
SCIRXDC (I)
SCITXDC (O)
EM1A4 (O)
EM1A5 (O)
EM1A6 (O)
EM1A7 (O)
EM1A8 (O)
EM1A9 (O)
EM1A10 (O)
EM1A11 (O)
EM1A12 (O)
EM1D31 (I/O)
EM1D30 (I/O)
EM1D29 (I/O)
EM1D28 (I/O)
EM1D27 (I/O)
EM1D26 (I/O)
EM1D25 (I/O)
EM1D24 (I/O)
EM1D23 (I/O)
EM1D22 (I/O)
EM1D21 (I/O)
EM1D20 (I/O)
EM1D19 (I/O)
EM1D18 (I/O)
EM1D17 (I/O)
EM1D16 (I/O)
EM1D15 (I/O)
EM1D14 (I/O)
EM1D13 (I/O)
EM1D12 (I/O)
EM1D11 (I/O)
EM1D10 (I/O)
EM1D9 (I/O)
EM1D8 (I/O)
EM1D7 (I/O)
EM1D6 (I/O)
EM1D5 (I/O)
EM1D4 (I/O)
EM1D3 (I/O)
EM1D2 (I/O)
EM1D1 (I/O)
EM1D0 (I/O)
EM1A13 (O)
EM1A14 (O)
EM1A15 (O)
EM1A16 (O)
SDAB (I/OD)
SCLB (I/OD)
SDAA (I/OD)
SCLA (I/OD)
EQEP2A (I)
EQEP2B (I)
EQEP2S (I/O)
EQEP2I (I/O)
OUTPUTXBAR1 (O)
OUTPUTXBAR2 (O)
OUTPUTXBAR3 (O)
OUTPUTXBAR4 (O)
EQEP3A (I)
EQEP3B (I)
EQEP3S (I/O)
EQEP3I (I/O)
SCIRXDD (I)
SCITXDD (O)
SCITXDA (O)
SCIRXDA (I)
SPISIMOC (I/O)
SPISOMIC (I/O)
SPICLKC (I/O)
SPISTEC (I/O)
SCITXDB (O)
SCIRXDB (I)
SCITXDC (O)
SCIRXDC (I)
SPICLKB (I/O)
SPISTEB (I/O)
SPISIMOB (I/O)
SPISOMIB (I/O)
CANRXA (I)
CANTXA (O)
SCIRXDA (I)
SCITXDA (O)
SDAB (I/OD)
XCLKOUT (O)
CANRXA (I)
CANTXA (O)
CANTXB (O)
CANRXB (I)
SCLB (I/OD)
SCITXDB (O)
SCIRXDB (I)
SCITXDC (O)
SCIRXDC (I)
SCITXDD (O)
SCIRXDD (I)
EQEP2A (I)
EQEP2B (I)
EQEP2S (I/O)
EQEP2I (I/O)
EM1CAS (O)
EM1RAS (O)
EM1DQM0 (O)
EM1DQM1 (O)
SCITXDA (O)
SCIRXDA (I)
SCITXDB (O)
SCIRXDB (I)
MDXB (O)
MDRB (I)
MCLKXB (I/O)
MFSXB (I/O)
SCITXDC (O)
7
15
11b
11b
11b
SCITXDA (O)
SCIRXDA (I)
SD1_D1 (I)
SD1_C1 (I)
SD1_D2 (I)
SD1_C2 (I)
SD1_D3 (I)
SD1_C3 (I)
SD1_D4 (I)
SD1_C4 (I)
SD2_D1 (I)
SD2_C1 (I)
SD2_D2 (I)
SD2_C2 (I)
SD2_D3 (I)
SD2_C3 (I)
SD2_D4 (I)
SD2_C4 (I)
SPISIMOA⁽³⁾ (I/O)
SPISOMIA⁽³⁾ (I/O)
SPICLKA⁽³⁾ (I/O)
SPISTEA⁽³⁾ (I/O)
SPISIMOB⁽³⁾ (I/O)
SPISOMIB⁽³⁾ (I/O)
SPICLKB⁽³⁾ (I/O)
SPISTEB⁽³⁾ (I/O)
SPISIMOC⁽³⁾ (I/O)
SPISOMIC⁽³⁾ (I/O)
SPICLKC⁽³⁾ (I/O)
SPISTEC⁽³⁾ (I/O)
MDXA (O)
MDRA (I)
MCLKXA (I/O)
MFSXA (I/O)
(3) High-Speed SPI-enabled GPIO mux option. This pin mux option is required when using the SPI in High-Speed Mode (HS_MODE = 1 in
SPICCR). This mux option is still available when not using the SPI in High-Speed Mode (HS_MODE = 0 in SPICCR).
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Terminal Configuration and Functions
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