TMS320F28075 Datasheet, PDF (140/182 Pages) Texas Instruments – Microcontrollers

TMS320F28075
SPRS902B – OCTOBER 2014 – REVISED OCTOBER 2015
5.10.5.1.3 Slave Mode External Timings Where Clock Phase = 0
Table 5-77. SPI Slave Mode External Timings Where Clock Phase = 0
NO.
12 t_c(SPC)S
13 ^tw(SPCH)S
t_w(SPCL)S
14 ^tw(SPCL)S
t_w(SPCH)S
15 ^{td(SPCH-SOMI)S}
t_{d(SPCL-SOMI)S}
t_{v(SPCH-SOMI)S}
16
t_{v(SPCL-SOMI)S}
19 ^{tsu(SIMO-SPCL)S}
t_{su(SIMO-SPCH)S}
t_{h(SPCL-SIMO)S}
20
t_{h(SPCH-SIMO)S}
t_{su(STE-SPCH)S}
25
t_{su(STE-SPCL)S}
26 ^{th(SPCL-STE)S}
t_h(SPCH-STE)S
Cycle time, SPICLK
Pulse duration, SPICLK high (clock polarity = 0)
Pulse duration, SPICLK low (clock polarity = 1)
Pulse duration, SPICLK low (clock polarity = 0)
Pulse duration, SPICLK high (clock polarity = 1)
Delay time, SPICLK high to SPISOMI valid (clock polarity = 0)
Delay time, SPICLK low to SPISOMI valid (clock polarity = 1)
Valid time, SPISOMI data valid after SPICLK high
(clock polarity = 0)
Valid time, SPISOMI data valid after SPICLK low
(clock polarity = 1)
Setup time, SPISIMO before SPICLK low (clock polarity = 0)
Setup time, SPISIMO before SPICLK high (clock polarity = 1)
Hold time, SPISIMO data valid after SPICLK low
(clock polarity = 0)
Hold time, SPISIMO data valid after SPICLK high
(clock polarity = 1)
Setup time, SPISTE valid before SPICLK high
(clock polarity = 0)
Setup time, SPISTE valid before SPICLK low
(clock polarity = 1)
Hold time, SPISTE invalid after SPICLK low (clock polarity = 0)
Hold time, SPISTE invalid after SPICLK high (clock polarity = 1)
MIN
4t_c(SYSCLK)
2t_c(SYSCLK) – 1
2t_c(SYSCLK) – 1
2t_c(SYSCLK) – 1
2t_c(SYSCLK) – 1
0
0
5
5
5
5
2t_c(SYSCLK)
2t_c(SYSCLK)
2t_c(SYSCLK)
2t_c(SYSCLK)
SPICLK
(clock polarity = 0)
SPICLK
(clock polarity = 1)
12
13
14
15
16
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MAX UNIT
ns
ns
ns
20
ns
20
ns
ns
ns
ns
ns
SPISOMI
SPISIMO
SPISTE
SPISOMI Data Is Valid
19
20
SPISIMO Data
Must Be Valid
25
26
Figure 5-66. SPI Slave Mode External Timing (Clock Phase = 0)
140 Specifications
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