LM3S1937 Datasheet, PDF (608/673 Pages) Texas Instruments – Stellaris® LM3S1937 Microcontroller

Signal Tables
Table 18-5. Signals by Pin Number (continued)
Pin Number
Pin Name
Pin Type Buffer Type^a Description
B10
CMOD1
I
TTL
CPU Mode bit 1. Input must be set to logic 0 (grounded); other
encodings reserved.
B11
PE2
I/O
TTL
GPIO port E bit 2.
PE1
B12
PWM5
I/O
TTL
GPIO port E bit 1.
O
TTL
PWM 5. This signal is controlled by PWM Generator 2.
C1
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
C2
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
C3
VDD25
-
Power Positive supply for most of the logic function, including the
processor core and most peripherals.
C4
GND
-
Power Ground reference for logic and I/O pins.
C5
GND
-
Power Ground reference for logic and I/O pins.
VDDA
C6
-
Power The positive supply for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
functions. VDDA pins must be supplied with a voltage that meets
the specification in “Recommended DC Operating
Conditions” on page 622, regardless of system implementation.
VDDA
C7
-
Power The positive supply for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
functions. VDDA pins must be supplied with a voltage that meets
the specification in “Recommended DC Operating
Conditions” on page 622, regardless of system implementation.
PH1
I/O
TTL
GPIO port H bit 1.
C8
PWM3
O
TTL
PWM 3. This signal is controlled by PWM Generator 1.
PH0
I/O
TTL
GPIO port H bit 0.
C9
PWM2
O
TTL
PWM 2. This signal is controlled by PWM Generator 1.
C10
PG7
I/O
TTL
GPIO port G bit 7.
PB2
C11
I2C0SCL
I/O
TTL
GPIO port B bit 2.
I/O
OD
I²C module 0 clock.
PB3
C12
I2C0SDA
I/O
TTL
GPIO port B bit 3.
I/O
OD
I²C module 0 data.
D1
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
D2
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
D3
VDD25
-
Power Positive supply for most of the logic function, including the
processor core and most peripherals.
D10
PH3
I/O
TTL
GPIO port H bit 3.
D11
PH2
I/O
TTL
GPIO port H bit 2.
PB1
D12
CCP2
I/O
TTL
GPIO port B bit 1.
I/O
TTL
Capture/Compare/PWM 2.
E1
PD4
I/O
TTL
GPIO port D bit 4.
E2
PD5
I/O
TTL
GPIO port D bit 5.
LDO
E3
-
Power Low drop-out regulator output voltage. This pin requires an external
capacitor between the pin and GND of 1 µF or greater. The LDO
pin must also be connected to the VDD25 pins at the board level
in addition to the decoupling capacitor(s).
608
June 18, 2012
Texas Instruments-Production Data