LM3S1937 Datasheet, PDF (176/673 Pages) Texas Instruments – Stellaris® LM3S1937 Microcontroller

System Control
Figure 5-5. Main Clock Tree
USEPWMDIV ^a
PWMDW ^a
MOSCDIS ^a
Main OSC
IOSCDIS^a
Internal
OSC
(12 MHz)
Internal
OSC
(30 kHz)
Hibernation
Module
(32.768 kHz)
XTAL^a
PWRDN ^b
PLL
(400 MHz)
÷4
OSCSRC^b,d
÷2
BYPASS ^b,d
÷ 25
USESYSDIV ^a,d
SYSDIV ^b,d
PWRDN
÷ 50
PWM Clock
System Clock
ADC Clock
CAN Clock
a. Control provided by RCC register bit/field.
b. Control provided by RCC register bit/field or RCC2 register bit/field, if overridden with RCC2 register bit USERCC2.
c. Control provided by RCC2 register bit/field.
d. Also may be controlled by DSLPCLKCFG when in deep sleep mode.
Note: The figure above shows all features available on all Stellaris® Fury-class devices. Not all peripherals may be
available on this device.
In the RCC register, the SYSDIV field specifies which divisor is used to generate the system clock
from either the PLL output or the oscillator source (depending on how the BYPASS bit in this register
is configured). When using the PLL, the VCO frequency of 400 MHz is predivided by 2 before the
divisor is applied. Table 5-5 shows how the SYSDIV encoding affects the system clock frequency,
depending on whether the PLL is used (BYPASS=0) or another clock source is used (BYPASS=1).
The divisor is equivalent to the SYSDIV encoding plus 1. For a list of possible clock sources, see
Table 5-4 on page 174.
176
June 18, 2012
Texas Instruments-Production Data