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LM3S1937 Datasheet, PDF (10/673 Pages) Texas Instruments – Stellaris® LM3S1937 Microcontroller
Table of Contents
List of Figures
Figure 1-1.
Figure 2-1.
Figure 2-2.
Figure 2-3.
Figure 2-4.
Figure 2-5.
Figure 2-6.
Figure 2-7.
Figure 3-1.
Figure 4-1.
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Figure 4-5.
Figure 5-1.
Figure 5-2.
Figure 5-3.
Figure 5-4.
Figure 5-5.
Figure 6-1.
Figure 6-2.
Figure 6-3.
Figure 7-1.
Figure 8-1.
Figure 8-2.
Figure 8-3.
Figure 9-1.
Figure 9-2.
Figure 9-3.
Figure 9-4.
Figure 10-1.
Figure 11-1.
Figure 11-2.
Figure 11-3.
Figure 11-4.
Figure 11-5.
Figure 12-1.
Figure 12-2.
Figure 12-3.
Figure 13-1.
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Figure 13-3.
Figure 13-4.
Figure 13-5.
Figure 13-6.
Figure 13-7.
Stellaris LM3S1937 Microcontroller High-Level Block Diagram ............................... 42
CPU Block Diagram ............................................................................................. 51
TPIU Block Diagram ............................................................................................ 52
Cortex-M3 Register Set ........................................................................................ 54
Bit-Band Mapping ................................................................................................ 74
Data Storage ....................................................................................................... 75
Vector Table ........................................................................................................ 81
Exception Stack Frame ........................................................................................ 83
SRD Use Example ............................................................................................... 97
JTAG Module Block Diagram .............................................................................. 156
Test Access Port State Machine ......................................................................... 160
IDCODE Register Format ................................................................................... 166
BYPASS Register Format ................................................................................... 166
Boundary Scan Register Format ......................................................................... 167
Basic RST Configuration .................................................................................... 170
External Circuitry to Extend Power-On Reset ....................................................... 171
Reset Circuit Controlled by Switch ...................................................................... 171
Power Architecture ............................................................................................ 173
Main Clock Tree ................................................................................................ 176
Hibernation Module Block Diagram ..................................................................... 232
Clock Source Using Crystal ................................................................................ 234
Clock Source Using Dedicated Oscillator ............................................................. 235
Flash Block Diagram .......................................................................................... 252
GPIO Port Block Diagram ................................................................................... 286
GPIODATA Write Example ................................................................................. 287
GPIODATA Read Example ................................................................................. 287
GPTM Module Block Diagram ............................................................................ 328
16-Bit Input Edge Count Mode Example .............................................................. 332
16-Bit Input Edge Time Mode Example ............................................................... 333
16-Bit PWM Mode Example ................................................................................ 334
WDT Module Block Diagram .............................................................................. 364
ADC Module Block Diagram ............................................................................... 388
Differential Sampling Range, VIN_ODD = 1.5 V ...................................................... 392
Differential Sampling Range, VIN_ODD = 0.75 V .................................................... 392
Differential Sampling Range, VIN_ODD = 2.25 V .................................................... 393
Internal Temperature Sensor Characteristic ......................................................... 394
UART Module Block Diagram ............................................................................. 425
UART Character Frame ..................................................................................... 426
IrDA Data Modulation ......................................................................................... 428
SSI Module Block Diagram ................................................................................. 466
TI Synchronous Serial Frame Format (Single Transfer) ........................................ 469
TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 470
Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 470
Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 471
Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 472
Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 472
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June 18, 2012
Texas Instruments-Production Data