LM3S1937 Datasheet, PDF (21/673 Pages) Texas Instruments – Stellaris® LM3S1937 Microcontroller

Stellaris^® LM3S1937 Microcontroller
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UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 435
UART Flag (UARTFR), offset 0x018 ................................................................................ 437
UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 439
UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 440
UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 441
UART Line Control (UARTLCRH), offset 0x02C ............................................................... 442
UART Control (UARTCTL), offset 0x030 ......................................................................... 444
UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 446
UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 448
UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 450
UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 451
UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 452
UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 454
UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 455
UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 456
UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 457
UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 458
UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 459
UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 460
UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 461
UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 462
UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 463
UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 464
UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 465
Synchronous Serial Interface (SSI) ............................................................................................ 466
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 479
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 481
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 483
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 484
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 486
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 487
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 489
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 490
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 491
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 492
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 493
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 494
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 495
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 496
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 497
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 498
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 499
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 500
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 501
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 502
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 503
Inter-Integrated Circuit (I²C) Interface ........................................................................................ 504
Register 1: I²C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 520
June 18, 2012
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