LM3S1937 Datasheet, PDF (285/673 Pages) Texas Instruments – Stellaris® LM3S1937 Microcontroller

Stellaris^® LM3S1937 Microcontroller
Table 8-5. GPIO Signals (108BGA) (continued)
Pin Name
Pin Number Pin Type Buffer Type^a Description
PH3
D10
I/O
TTL
GPIO port H bit 3.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
8.2 Functional Description
Important: All GPIO pins are tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0,
and GPIOPUR=0), with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]).
The JTAG/SWD pins default to their JTAG/SWD functionality (GPIOAFSEL=1,
GPIODEN=1 and GPIOPUR=1). A Power-On-Reset (POR) or asserting RST puts both
groups of pins back to their default state.
While debugging systems where PB7 is being used as a GPIO, care must be taken to
ensure that a low value is not applied to the pin when the part is reset. Because PB7
reverts to the TRST function after reset, a Low value on the pin causes the JTAG
controller to be reset, resulting in a loss of JTAG communication.
Each GPIO port is a separate hardware instantiation of the same physical block (see Figure
8-1 on page 286). The LM3S1937 microcontroller contains eight ports and thus eight of these physical
GPIO blocks.
June 18, 2012
285
Texas Instruments-Production Data