LM3S1937 Datasheet, PDF (18/673 Pages) Texas Instruments – Stellaris® LM3S1937 Microcontroller

Table of Contents
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ....................... 213
Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ................................... 215
Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 217
Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 219
Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 221
Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 223
Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 225
Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 227
Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 228
Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 230
Hibernation Module ..................................................................................................................... 231
Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000 ......................................................... 240
Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 ....................................................... 241
Register 3: Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 ....................................................... 242
Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C ........................................................... 243
Register 5: Hibernation Control (HIBCTL), offset 0x010 ..................................................................... 244
Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014 ............................................................. 246
Register 7: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 .................................................. 247
Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................ 248
Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020 ............................................................. 249
Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024 ............................................................... 250
Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C ............................................................ 251
Internal Memory ........................................................................................................................... 252
Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 258
Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 259
Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 260
Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 262
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 263
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 264
Register 7: USec Reload (USECRL), offset 0x140 ............................................................................ 266
Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 267
Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 268
Register 10: User Debug (USER_DBG), offset 0x1D0 ......................................................................... 269
Register 11: User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 270
Register 12: User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 271
Register 13: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 272
Register 14: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 273
Register 15: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 274
Register 16: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 275
Register 17: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 276
Register 18: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 277
General-Purpose Input/Outputs (GPIOs) ................................................................................... 278
Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 293
Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 294
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 295
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 296
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 297
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 298
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June 18, 2012
Texas Instruments-Production Data