TLK1211 Datasheet, PDF (6/21 Pages) Texas Instruments – ETHERNET TRANSCEIVERS

TLK1211RCP
SLLS658D – SEPTEMBER 2006 – REVISED APRIL 2011
TXP, TXN
TD(0−9)
10-Bit Code
www.ti.com
Measured 10-Bits
Next 10-Bit Code
t_{d(Tx latency)}
b7 b8 b9 b0 b1 b2 b3
REFCLK
Figure 1. Transmitter Latency Full Rate Mode
Data Reception
The receiver portion deserializes the differential serial data. The serial data is retimed based on an interpolated
clock generated from the reference clock. The serial data is then aligned to the 10-bit word boundaries and
presented to the protocol controller along with receive byte clocks (RBC0 and RBC1).
Receiver Clock Select Mode
There are two modes of operation for the parallel bus: 1) the 10-bit (TBI) mode and 2) 5-bit (DDR) mode. When
in TBI mode, there are two user-selectable clock modes that are controlled by the RBCMODE terminal: 1)
full-rate clock on RBC0 and 2) half-rate clocks on RBC0 and RBC1. When in the DDR mode, only a full-rate
clock is available on RBC0; see Table 2.
MODESEL
0
0
1
1
Table 2. Mode Selection
RBCMODE
0
1
0
1
MODE
TBI half-rate
TBI full-rate
DDR
DDR
RECEIVE BYTE
CLOCK
30–65 MHz
60–130 MHz
60–130 MHz
60–130 MHz
In the half-rate mode, two receive byte clocks (RBC0 and RBC1) are 180 degrees out of phase and operate at
one-half the data rate. The clocks are generated by dividing down the recovered clock. The received data is
output with respect to the two receive byte clocks (RBC0 and RBC1) allowing a protocol device to clock the
parallel bytes using the RBC0 and RBC1 rising edges. The outputs to the protocol device, byte 0 of the received
data is valid on the rising edge of RBC1. See the timing diagram shown in Figure 2.
RBC0
RBC1
SYNC
RD(0-9)
t_d(S)
t_d(S)
t_d(H)
t_d(H)
K28.5
DXX.X
DXX.X
DXX.X
K28.5
DXX.X
Figure 2. Synchronous Timing Characteristics Waveforms (TBI Half-Rate Mode)
In the normal-rate mode, only RBC0 is used and operates at full data rate (that is, 1.25-Gbps data rate produces
a 125-MHz clock). The received data is output with respect to the rising edge of RBC0. RBC1 is low in this
mode. See the timing diagram shown in Figure 3.
6
Submit Documentation Feedback
Copyright © 2006–2011, Texas Instruments Incorporated
Product Folder Link(s): TLK1211RCP