TLK1211 Datasheet, PDF (12/21 Pages) Texas Instruments – ETHERNET TRANSCEIVERS

TLK1211RCP
SLLS658D – SEPTEMBER 2006 – REVISED APRIL 2011
www.ti.com
TRANSMITTER/RECEIVER CHARACTERISTICS
PARAMETER
TEST CONDITIONS
V_OD
V_(cm)
V_OD = |TxD-TxN|
Transmit common mode voltage range
Receiver input voltage requirement,
V_ID = |RxP - RxN|
Receiver common mode voltage range, (RxP
+ RxN)/2
R_t = 50Ω
R_t = 50Ω
I_lkg(R)
C_I
t_(TJ)
t_(DJ)
t_r, t_f
Receiver input leakage current
Receiver input capacitance
Serial data total jitter (peak-to-peak)
Serial data deterministic jitter (peak-to-peak)
Differential signal rise, fall time (20% to 80%)
Differential output jitter, Random +
deterministic, PRBS pattern,
R_ω = 125 MHz
Differential output jitter, Random +
deterministic, PRBS pattern,
R_ω = 106.25 MHz
Differential output jitter, PRBS pattern,
R_ω = 125 MHz
R_L = 50 Ω, C_L = 5 pF, See Figure 8
and Figure 7
Serial data jitter tolerance minimum required
eye opening, (per IEEE-802.3 specification at
1.25Gbps and per CPRI 2.0 specification at
614.4Mbps)
Receiver data acquisition lock time from
powerup
Differential input jitter, Random +
deterministic, R_ω = 125 MHz
Differential input jitter, Random + .4 UI
deterministic, R_ω = 61.44MHz
Data re-lock time from application of valid
input data stream
.75 UI jitter closure with random data
@ 1.25 Gbps
.20 UI jitter closure with 01010.. data
@ 1.25Gbps
t_{d(Tx latency)}
Tx latency
TBI modes
DDR mode
See Figure 1
TBI modes See Figure 6
DDR mode
t_{d(Rx latency)}
Rx latency
TBI mode
DDR mode
600–620 Mbps
600–620 Mbps
TBI mode
1228.8 Mbps
DDR mode 1228.8 Mbps
(1) UI = serial bit time
MIN
600
1000
TYP
800
1250
MAX
1100
1400
UNIT ⁽¹⁾
mV
mV
200
1600 mV
1000 1250 2250 mV
-350
350 μA
2
pF
0.24 UI
0.2 UI
0.10 UI
100
250 ps
0.25
UI
0.34
UI
500 μs
256 ns
128 ns
20
22
UI
30
32
18
24
17
23
18
21
UI
17
22
19
23
18
23
TX+
t_r
TX−
80% ^{∼ V}
50%
20% _{∼ V}
t_f
∼V
80%
50%
20% ∼ V
t_f
80%
VOD
20%
t_r
∼ 1V
0V
∼ −1V
Figure 7. Differential and Common-Mode Output Voltage Definitions
12
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