TLK1211 Datasheet, PDF (2/21 Pages) Texas Instruments – ETHERNET TRANSCEIVERS

TLK1211RCP
SLLS658D – SEPTEMBER 2006 – REVISED APRIL 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DESCRIPTION CONTINUED
The primary application of the transceiver is to provide building blocks for point-to-point baseband data
transmission over controlled impedance media of 50 Ω. The transmission media can be printed-circuit board
traces, copper cables, or fiber-optical media. The ultimate rate and distance of data transfer is dependent upon
the attenuation characteristics of the media and the noise coupling to the environment.
The transceiver performs the data serialization, deserialization, and clock extraction functions for a physical layer
interface device. The transceiver operates at 1.25 Gbps (typical), providing up to 1 Gbps of data bandwidth over
a copper or optical media interface.
The transceiver supports both the defined 10-bit interface (TBI) and a reduced 5-bit interface utilizing double data
rate (DDR) clocking. In the TBI mode the serializer/deserializer (SERDES) accepts 10-bit wide 8b/10b parallel
encoded data bytes. The parallel data bytes are serialized and transmitted differentially at PECL compatible
voltage levels. The SERDES extracts clock information from the input serial stream and deserializes the data,
outputting a parallel 10-bit data byte.
In the DDR mode the parallel interface accepts 5-bit wide 8b/10b encoded data aligned on both the rising and
falling edges of the reference clock. The data is clocked most significant bit first (bits 0–4 of the 8b/10b encoded
data) on the rising edge of the clock and the least significant bits (bits 5–9 of the 8b/10b encoded data) are
clocked on the falling edge of the clock.
The transceiver provides a comprehensive series of built-in tests for self-test purposes including loopback and
pseudorandom binary sequence (PRBS) generation and verification. An IEEE 1149.1 JTAG port is also
supported.
The transceiver is housed in a high-performance, thermally enhanced, 64-pin VQFP PowerPAD package. Use of
the PowerPAD package does not require any special considerations except to note that the PowerPAD, which is
an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor. It is
recommended that the device PowerPAD be soldered to the thermal land on the board.
The transceiver is characterized for operation from –40°C to 85°C.
The transceiver uses a 2.5-V supply. The I/O section is 3.3-V compatible. With a 2.5-V supply the chipset is very
power-efficient, dissipating less than 250 mW typical power when operating at 1.25 Gbps.
The transceiver is designed to be hot plug capable. A power-on reset causes RBC0, RBC1, the parallel output
signal terminals, TXP, and TXN to be held in a high-impedance state.
Differences Between TLK1211RCP and TNETE2201
The TLK1211RCP transceiver is the functional equivalent of the TNETE2201. There are several differences
between the devices as noted below. See Figure 12 in the Application Information section for an example of a
typical application circuit.
• The V_CC is 2.5 V for the TLK1211RCP vs 3.3 V for TNETE2201.
• The PLL filter capacitors on terminals 16, 17, 48, and 49 of the TNETE2201 are no longer required. The
TLK1211RCP uses these terminals to provide added test capabilities. The capacitors, if present, do not affect
the operation of the device.
• No pulldown resistors are required on the TXP/TXN outputs.
• TLK1211RCP has faster re-lock time compared to the TLK1201A and TNETE2201B.
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