TLK1211 Datasheet, PDF (3/21 Pages) Texas Instruments – ETHERNET TRANSCEIVERS

TLK1211RCP
www.ti.com
SLLS658D – SEPTEMBER 2006 – REVISED APRIL 2011
Table 1. AVAILABLE OPTIONS⁽¹⁾
T_A
–40°C to 85°C
PACKAGE
PLASTIC QUAD FLAT PACK (RCP)
TLK1211RCP
(1) For the most current package and ordering information, see the
Package Option Addendum at the end of this document, or see the
TI website at www.ti.com.
BLOCK DIAGRAM
PRBSEN
LOOPEN
PRBS
Generator
TD(0-9)
10 Bit
Registers
2:1
MUX
Parallel to
Serial
Clock
TXP
TXN
REFCLK
MODESEL
ENABLE
TESTEN
RBC1
RBC0
SYNC/PASS
Control
Logic
PRBS
Verification
Phase Generator
Interpolator
and
Clock Extraction
Clock
2:1
MUX
Clock
RD(0-9)
SYNCEN
RBCMODE
JTMS
JTRSTN
JTDI
TCK
Serial to Parallel
and
Comma Detect
JTAG
Control
Register
2:1
MUX
JTDO
Data
RXP
RXN
LOS
TERMINAL
NAME
NO.
SIGNAL
MODESEL
15
LOS
26
Terminal Functions
I/O
DESCRIPTION
I
P/D ⁽¹⁾
O
Mode select. This terminal selects between the 10-bit interface and a reduced 5-bit DDR
interface. When low, the 10-bit interface (TBI) is selected. When pulled high, the 5-bit DDR mode
is selected. The default mode is the TBI.
Loss of signal. Indicates a loss of signal on the high-speed differential inputs RXP and RXN.
If the magnitude of RXP-RXN > 150 mV, then LOS = 1 which is a valid input signal.
If the magnitude of RXP-RXN > 50 mV and < 150 mV, then LOS is undefined.
If the magnitude of RXP-RXN < 50 mV, then LOS = 0 which is a loss of signal.
Note: Above LOS conditions are specified only for Input Common Mode Voltage (RXP+RXN)/2 ≥
1.25V
(1) P/D = Internal pulldown
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