TLK1211 Datasheet, PDF (13/21 Pages) Texas Instruments – ETHERNET TRANSCEIVERS

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TLK1211RCP
SLLS658D – SEPTEMBER 2006 – REVISED APRIL 2011
C_L
5 pF
50 Ω
50 Ω
C_L
5 pF
Figure 8. Transmitter Test Setup
LVTTL OUTPUT SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
t_r(RBC)
t_f(RBC)
t_r
t_f
t_su(D1)
Clock rise time
Clock fall time
Data rise time
Data fall time
Data setup time (RD0–RD9), Data
valid prior to RBC0 rising
80% to 20% output voltage, C = 5 pF (see
Figure 9)
TBI normal mode, (see Figure 3)
t_h(D1)
Data hold time (RD0–RD9), Data valid
after RBC0 rising
TBI normal mode, (see Figure 3)
t_su(D2)
t_h(D2)
t_su(D3)
t_h(D3)
Data setup time (RD0–RD4)
Data hold time (RD0–RD4)
Data setup time (RD0–RD9)
Data hold time (RD0–RD9)
DDR mode, R_ω = 125 MHz, (see Figure 4)
DDR mode, R_ω = 125 MHz, (see Figure 4)
TBI half-rate mode, R_ω = 125 MHz, (see Figure 2)
TBI half-rate mode, R_ω = 125 MHz, (see Figure 2)
MIN TYP
0.3
0.3
0.3
0.3
2.5
MAX
1.5
1.5
1.5
1.5
UNIT
ns
ns
ns
2
ns
2
ns
0.8
ns
2.5
ns
1.5
ns
CLOCK
1.4 V
t_r
t_f
DATA
t_r
80%
50%
20%
t_f
2V
0.8 V
Figure 9. TTL Data I/O Valid Levels for AC Measurement
TRANSMITTER TIMING REQUIREMENTS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
t_su(D4)
t_h(D4)
t_su(D5)
t_h(D5)
t_r, t_f
Data setup time (TD0–TD9)
Data hold time (TD0–TD9)
Data setup time (TD0–TD9)
Data hold time (TD0–TD9)
TD[0,9] data rise and fall time
TBI modes
DDR modes
See Figure 9
MIN TYP MAX UNIT
1.6
ns
0.8
0.7
ns
0.5
2 ns
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