TLK1211 Datasheet, PDF (5/21 Pages) Texas Instruments – ETHERNET TRANSCEIVERS

TLK1211RCP
www.ti.com
SLLS658D – SEPTEMBER 2006 – REVISED APRIL 2011
TERMINAL
NAME
NO.
LOOPEN
19
I/O
I
P/D ⁽³⁾
PRBSEN
16
I
P/D ⁽³⁾
TCK
TESTEN
POWER
VDD
VDDA
VDDPLL
GROUND
GND
GNDA
GNDPLL
49
I
17
I
P/D ⁽³⁾
5, 10,
20, 23,
29, 37,
42, 50,
63
53, 57,
59, 60
18
Supply
Supply
Supply
1, 14,
21,25,
33, 46
51, 58
64
Ground
Ground
Ground
(3) P/D = Internal pulldown
Terminal Functions (continued)
DESCRIPTION
Loop enable. When LOOPEN is high (active), the internal loop-back path is activated. The
transmitted serial data is directly routed to the inputs of the receiver. This provides a self-test
capability in conjunction with the protocol device. The TXP and TXN outputs are held in a
high-impedance state during the loop-back test. LOOPEN is held low during standard operational
state with external serial outputs and inputs active.
PRBS enable. When PRBSEN is high, the PRBS generation circuitry is enabled. The PRBS
verification circuit in the receive side is also enabled. A PRBS signal can be fed to the receive
inputs and checked for errors, that are reported by the SYNC/PASS terminal indicating low.
Test clock. IEEE1149.1 (JTAG)
Manufacturing test terminal
Digital logic power. Provides power for all digital circuitry and digital I/O buffers.
Analog power. VDDA provides power for the high-speed analog circuits, receiver, and transmitter
PLL power. Provides power for the PLL circuitry. This terminal requires additional filtering.
Digital logic ground. Provides a ground for the logic circuits and digital I/O buffers.
Analog ground. GNDA provides a ground for the high-speed analog circuits RX and TX.
PLL ground. Provides a ground for the PLL circuitry.
DETAILED DESCRIPTION
Data Transmission
This device supports both the defined 10-bit interface (TBI) and a reduced 5-bit interface utilizing DDR clocking.
When MODESEL is low, the TBI mode is selected. When MODESEL is high, the DDR mode is selected.
In the TBI mode, the transmitter portion registers incoming 10-bit wide data words (8b/10b encoded data,
TD0–TD9) on the rising edge of REFCLK. The REFCLK is also used by the serializer, which multiplies the clock
by a factor of 10, providing a signal that is fed to the shift register. The 8b/10b encoded data is transmitted
sequentially bits 0 through 9 over the differential high-speed I/O channel.
In the DDR mode, the transmitter accepts 5-bit wide 8b/10b encoded data on pins TD0–TD4. In this mode, data
is aligned to both the rising and falling edges of REFCLK. The data is then formed into a 10-bit wide word and
sent to the serializer. The rising edge REFCLK clocks in bits 0–4, and the falling edge of REFCLK clocks in bits
5–9. Bit 0 is the first bit transmitted.
Transmission Latency
Data transmission latency is defined as the delay from the initial 10-bit word load to the serial transmission of bit
9. The minimum latency in TBI mode is 20 bit times. The maximum latency in TBI mode is 22 bit times. The
minimum latency in DDR mode is 30 bit times, and maximum latency in DDR mode is 32 bit times.
Copyright © 2006–2011, Texas Instruments Incorporated
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