SPNA135A Datasheet, PDF (6/15 Pages) Texas Instruments – Compatibility Considerations: TMS570LS20x/10x to TMS570LS31x/21x

Module-Level Feature Differences
www.ti.com
3.12 CPU Self-Test Controller (STC)
The main enhancements to the STC module of the LS31x/21x as compared to the LS20x/10x are:
• Added the ability to check the STC comparator logic itself before enabling the CPU self-test
• Optimized the CPU self-test patterns to get a higher coverage for a given number of test intervals
• LS31x/21x requires 24 test intervals (32768 cycles total) to get CPU coverage > 90%; LS20x/10x
required 32 test intervals (49698 cycles total)
• CPU self-test can be run at CPU clock speeds up to 90 MHz on LS31x/21x; this was limited to 53.33
MHz on LS20x/10x.
3.13 System Module (SYS)
The main enhancements to the SYS module of the LS31x/21x as compared to the LS20x/10x are:
• Added control to select between main oscillator and VCLK as input to the external clock prescaler
(ECP)
• Enhanced clock test mode that allows all clock sources and domains to be brought out on device
terminals for debug purposes
6
Compatibility Considerations: TMS570LS20x/10x to TMS570LS31x/21x
Copyright © 2011, Texas Instruments Incorporated
SPNA135A – October 2011
Submit Documentation Feedback