SPNA135A Datasheet, PDF (10/15 Pages) Texas Instruments – Compatibility Considerations: TMS570LS20x/10x to TMS570LS31x/21x

Analog IP Differences
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5 Analog IP Differences
The following sections highlight the significant differences in the analog IP between the LS20x/10x and
LS31x/21x microcontrollers.
5.1 Flash Bank and Pump
The most significant changes to the Flash pump and Flash bank are listed below. These have no impact
to the application software or hardware development.
• The Flash pump on the LS31x/21x allows up to 144 bits to be programmed simultaneously versus 32
on LS20x/10x, which allows faster programming of Flash.
• The Flash pump on LS31x/21x implements a glitch filter on the power-on reset signal, which has a
minimum filter time of 500 ns versus 35 ns on LS20x/10x.
• The Flash bank on LS31x/21x supports a maximum CPU clock frequency of 45 MHz for a single-cycle
Flash read access; this was limited to 36 MHz on LS20x/10x.
5.2 Phase-Locked-Loops (PLL1, PLL2)
The LS31x/21x as well as the LS20x/10x microcontrollers contain two separate PLL instances: PLL1 and
PLL2. Figure 1 and Figure 2 show high-level block diagrams for the PLLs on LS20x/10x and LS31x/21x
microcontrollers.
OSCIN
/NR
INTCLK
/1 to /64
PLL
VCOCLK
/OD
/1 to /8
post_ODCLK
/R
/1 to /32
PLLCLK
/NF
/1 to /256
f_PLLCLK = (f_OSCIN / NR) * NF / (OD * R)
OSCIN
/NR2
/1 to /64
INTCLK2
PLL#2
VCOCLK2
/OD2
/1 to /8
post_ODCLK2
/R2
/1 to /32
PLL2CLK
/NF2
/1 to /256
f_PLL2CLK = (f_OSCIN / NR2) * NF2 / (OD2 * R2)
Figure 1. PLLs on TMS570LS31x/21x
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Compatibility Considerations: TMS570LS20x/10x to TMS570LS31x/21x
Copyright © 2011, Texas Instruments Incorporated
SPNA135A – October 2011
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