SPNA135A Datasheet, PDF (11/15 Pages) Texas Instruments – Compatibility Considerations: TMS570LS20x/10x to TMS570LS31x/21x

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Analog IP Differences
OSCIN
/NR
INTCLK
/1 to /64
PLL
VCOCLK
/OD
/1 to /8
/NF
/92 to /184
post_ODCLK
/R
/1 to /32
PLLCLK
f_PLLCLK = (f_OSCIN / NR) * NF / (OD * R)
OSCIN
/NR2
/1 to /2
INTCLK2
PLL#2
VCOCLK2
/R2
/1 to /8
PLL2CLK
/NF2
/1 to /15
f_PLL2CLK = (f_OSCIN / NR2) * NF2 / R2
Figure 2. PLLs on TMS570LS20x/10x
There are significant differences in the values of the multipliers and dividers that determine the PLL output
frequency between the LS20x/10x and LS31x/21x microcontrollers, as shown in Figure 1 and Figure 2. It
is still important to note that any PLL control register setting used on the LS20x/10x microcontrollers can
be used as-is on the LS31x/21x as long as frequency modulation is not enabled.
The other differences between the PLLs on LS20x/10x and LS31x/21x microcontrollers are now
summarized.
• The PLL1 on LS20x/10x can be powered with the spread-spectrum mode enabled; the SS mode must
only be enabled after the FMzPLL powers up on LS31x/21x.
• The PLL1 power-up time for LS20x/10x is 4639 INTCLK cycles; this time is 1024 INTCLK cycles + 134
OSCIN cycles on LS31x/21x.
• The PLL2 power-up time for LS20x/10x is 30 µs regardless of the input clock frequencies; this time is
1024 INTCLK2 cycles + 134 OSCIN cycles on LS31x/21x.
• The INTCLK frequency on LS20x/10x is limited to the range 1.63 MHz to 6.53 MHz; this range is 430
kHz to 100 MHz on LS31x/21x.
• The INTCLK2 frequency on LS20x/10x is required to be in the range 10 MHz to 100 MHz; this range is
430 kHz to 100 MHz on LS31x/21x.
• The VCOCLK frequency on LS20x/10x is limited to the range 120 MHz to 500 MHz; this range is 110
MHz to 550 MHz on LS31x/21x.
• The VCOCLK2 frequency on LS20x/10x is required to be in the range 10 MHz to 250 MHz; this range
is 110 MHz to 550 MHz on LS31x/21x.
• The post_ODCLK frequency on LS20x/10x is limited to the range 120 MHz to 160 MHz; this range is
110 MHz to 400 MHz on LS31x/21x for both post_ODCLK and post_ODCLK2.
• The PLLCLK frequency on LS20x/10x is limited to a max of 160 MHz; this value is 180 MHz on
LS31x/31x.
• The PLL2CLK frequency on LS20x/10x is limited to a max of 160 MHz; this value is 180 MHz on
LS31x/21x.
• The PLL1 slip on LS20x/10x cannot be filtered; the LS31x/21x has a 6-bit programmable slip filter that
runs on HF LPO.
• Once a PLL1 slip is indicated on LS20x/10x, the PLL1 output clock cannot be used for any clock
domain. On the LS31x/21x, the application has an option to try and restart the PLL so that the
application can resume using the PLL output for any clock domain.
SPNA135A – October 2011
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Compatibility Considerations: TMS570LS20x/10x to TMS570LS31x/21x
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