SPNA135A Datasheet, PDF (4/15 Pages) Texas Instruments – Compatibility Considerations: TMS570LS20x/10x to TMS570LS31x/21x

Module-Level Feature Differences
3 Module-Level Feature Differences
The following sections highlight the significant module-level enhancements/differences on the
TMS570LS31x/21x series of microcontrollers.
www.ti.com
3.1 12-bit Analog-to-Digital Converter (ADC)
The main enhancements to the ADC digital interface module of LS31x/21x as compared to LS20x/10x are:
• 10/12-bit mode allows application to configure the module as a true 10-bit converter (10 cycles for
conversion)
• Low-power mode allows the ADC to automatically enter power-saving mode when no conversions are
pending
• Event triggering allows the use of both rising and falling edges of selected event to trigger conversions
• DMA support allows the application to generate DMA request on "group conversion end"
• Results RAM allows the application to not reset the result memory for a conversion group when new
channel selection is made for that group
3.2 Core Compare Module (CCM-R4)
The two CPUs on the LS31x/21x microcontrollers are 2 GCLK cycles out of phase. The two CPUs are 1.5
GCLK cycles out of phase on the LS20x/10x series. This is completely transparent to the application
software or hardware designer.
3.3 External Memory Interface (EMIF)
The EMIF on LS31x/21x allows interfacing to asynchronous memories and an external SDRAM module.
The EMIF on LS20x/10x only allowed interfacing to external asynchronous memories.
3.4 Error Signaling Module (ESM)
The ESM module on the LS31x/21x microcontrollers can now support up to 64 channels for group1 error
conditions. This is functionally compatible and enhanced compared to the ESM module on LS20x/10x
microcontrollers which only supported 32 channels for group1 error conditions.
3.5 Global Clock Module (GCM)
Main enhancements to the GCM on the LS31x/21x as compared to the LS20x/10x are:
• Support for additional clock domains: VCLK3, AVCLK3, and AVCLK4. The application needs to
configure the clock source selection for these clock domains if the associated functionality is being
used in the application. To identify the functions that use these new clock domains, check the
device-specific datasheet and TRM.
• Ability to observe the PLL output clock on ECLK while the PLL is still acquiring lock to the reference
clock
3.6 Local Interconnect Network Controller (LIN)
The LIN controller module on the LS31x/21x microcontrollers is enhanced to support conformance to LIN
specification version 2.1, which is backwards compatible to the LIN protocol specification version 2.0. The
LIN module on LS20x/10x microcontrollers is conformant to LIN specification version 2.0.
3.7 Low-Power Oscillator / Clock Detector (LPOCLKDET)
The main enhancements to the LPOCLKDET module of the LS31x/21x as compared to the LS20x/10x
are:
• Trim settings for HF LPO and LF LPO increased from a 4-bit value to a 5-bit value, offering greater
granularity for controlling the LPO output frequencies
• Improved availability; added ability to restart the main oscillator whenever an oscillator failure is
detected
4
Compatibility Considerations: TMS570LS20x/10x to TMS570LS31x/21x
Copyright © 2011, Texas Instruments Incorporated
SPNA135A – October 2011
Submit Documentation Feedback