MSP430FR2111 Datasheet, PDF (6/75 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP430FR2111, MSP430FR2110
SLASE78A – AUGUST 2016 – REVISED AUGUST 2016
4 Terminal Configuration and Functions
4.1 Pin Diagrams
Figure 4-1 shows the pinout of the 16-pin PW package.
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P1.1/UCA0CLK/ACLK/C1/A1 1
P1.0/UCA0STE/SMCLK/C0/A0/Veref+ 2
TEST/SBWTCK 3
RST/NMI/SBWTDIO 4
DVCC 5
DVSS 6
P2.7/TB0CLK/XIN 7
P2.6/MCLK/XOUT 8
MSP430FR2111IPW16
MSP430FR2110IPW16
16 P1.2/UCA0RXD/UCA0SOMI/TB0TRG/C2/A2/Veref-
15 P1.3/UCA0TXD/UCA0SIMO/C3/A3
14 P1.4/UCA0STE/TCK/A4
13 P1.5/UCA0CLK/TMS/A5
12 P1.6/UCA0RXD/UCA0SOMI/TB0.1/TDI/TCLK/A6
11 P1.7/UCA0TXD/UCA0SIMO/TB0.2/TDO/A7/VREF+
10 P2.0/TB0.1/COUT
9 P2.1/TB0.2
Figure 4-1. 16-Pin PW (TSSOP) (Top View)
Figure 4-2 shows the pinout of the 24-pin RLL package.
TEST/SBWTCK
RST/NMI/SBWTDIO
DVCC
DVSS
P2.7/TB0CLK/XIN
NC
24 23 22 21 20 19
1
18
2
17
3 _{MSP430FR2111IRLL} 16
4 ^{MSP430FR2110IRLL} 15
5
14
6
13
7 8 9 10 11 12
NC
P1.3/UCA0TXD/UCA0SIMO/C3/A3
P1.4/UCA0STE/TCK/A4
P1.5/UCA0CLK/TMS/A5
P1.6/UCA0RXD/UCA0SOMI/TB0.1/TDI/TCLK/A6
P1.7/UCA0TXD/UCA0SIMO/TB0.2/TDO/A7/VREF+
Figure 4-2. 24-Pin RLL (QFN) (Top View)
6
Terminal Configuration and Functions
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