MSP430FR2111 Datasheet, PDF (11/75 Pages) Texas Instruments – Mixed-Signal Microcontrollers

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MSP430FR2111, MSP430FR2110
SLASE78A – AUGUST 2016 – REVISED AUGUST 2016
4.4 Pin Multiplexing
Pin multiplexing for these devices is controlled by both register settings and operating modes (for
example, if the device is in test mode). For details of the settings for each pin and schematics of the
multiplexed ports, see Section 6.11.15.
4.5 Connection of Unused Pins
Table 4-3 lists the correct termination of unused pins.
Table 4-3. Connection of Unused Pins⁽¹⁾
PIN
POTENTIAL
COMMENT
Px.0 to Px.7
RST/NMI
Open
DVCC
Set to port function, output direction (PxDIR.n = 1)
47-kΩ pullup or internal pullup selected with 10-nF (1.1 nF) pulldown⁽²⁾
TEST
Open
This pin always has an internal pulldown enabled.
(1) Any unused pin with a secondary function that is shared with general-purpose I/O should follow the Px.0 to Px.7 unused pin connection
guidelines.
(2) The pulldown capacitor should not exceed 1.1 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode with TI tools like
FET interfaces or GANG programmers.
4.6 Buffer Type
Table 4-4 defines the pin buffer types that are listed in Table 4-1.
BUFFER TYPE NOMINAL
(STANDARD) VOLTAGE
LVCMOS
3.0 V
Analog
3.0 V
Power (DVCC)
3.0 V
Power (AVCC)
3.0 V
(1) Only for input pins
Table 4-4. Buffer Type
HYSTERESIS
Y ⁽¹⁾
No
No
No
PU OR PD
Programmable
No
No
No
NOMINAL
PU OR PD
STRENGTH
(µA)
See
Section 5.13.4
N/A
N/A
N/A
OUTPUT
DRIVE
STRENGTH
(mA)
OTHER
CHARACTERISTICS
See
Section 5.13.4.1
N/A
See analog modules in
Section 5 for details.
N/A
SVS enables hysteresis on
DVCC.
N/A
Copyright © 2016, Texas Instruments Incorporated
Terminal Configuration and Functions
11
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