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MSP430F6638 Datasheet, PDF (6/126 Pages) Texas Instruments – Mixed-Signal Microcontrollers
MSP430F6638, MSP430F6637, MSP430F6636, MSP430F6635
MSP430F6634, MSP430F6633, MSP430F6632, MSP430F6631, MSP430F6630
SLAS566E – JUNE 2010 – REVISED DECEMBER 2015
www.ti.com
7.1 Device Support..................................... 112
7.2 Documentation Support............................ 115
7.3 Related Links ...................................... 115
7.4 Community Resources............................. 116
7.5 Trademarks ........................................ 116
7.6 Electrostatic Discharge Caution ................... 116
7.7 Export Control Notice .............................. 116
7.8 Glossary............................................ 116
8 Mechanical, Packaging, and Orderable
Information ............................................. 116
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from August 5, 2013 to December 8, 2015
Page
• Document format and organization changes throughout, including addition of section numbering........................ 1
• Moved all functional block diagrams to Section 1.4, Functional Block Diagrams ............................................ 3
• Added USB column to Table 3-1, Family Members ............................................................................. 7
• Added Section 3, Device Comparison, and moved Table 3-1, Family Members to it ....................................... 7
• Added "Port U is supplied by the LDOO rail" to the PU.0 and PU.1 descriptions in Table 4-1, Signal Descriptions .. 17
• Moved all electrical specifications to Section 5 ................................................................................. 19
• Added Section 5.2, ESD Ratings.................................................................................................. 19
• Added note to CVCORE............................................................................................................... 19
• Added note to RPull .................................................................................................................. 24
• Changed TYP value of CL,eff with Test Conditions of "XTS = 0, XCAPx = 0" from 2 pF to 1 pF ......................... 28
• In VBAT3 parameter description, changed from "VBAT3 ≠ VBAT/3" to "VBAT3 = VBAT/3" ........................................ 35
• Changed from fDAC12_0OUT to fDAC12_1OUT in the first row of the Test Conditions for the "Channel-to-channel
crosstalk" parameter ................................................................................................................ 52
• Changed the value of DAC12_xDAT from 7F7h to F7Fh and changed the x-axis label from fToggle to 1/fToggle in
Figure 5-22, Crosstalk Test Conditions .......................................................................................... 52
• Added note to RPUR ................................................................................................................. 54
• Corrected the spelling of the MRG bits in the fMCLK,MRG parameter ........................................................... 56
• Removed RTC_B from LPM4.5 wake-up options............................................................................... 59
• Throughout document, changed all instances of "bootstrap loader" to "bootloader" ....................................... 62
• Added the paragraph that starts "The application report Using the MSP430 RTC_B..." .................................. 66
• Corrected names of interrupt events PMMSWBOR (BOR) and PMMSWPOR (POR) in Table 6-11, System
Module Interrupt Vector Registers ................................................................................................ 67
• Corrected spelling of NMIIFG (added missing "I") in Table 6-11, System Module Interrupt Vector Registers.......... 67
• Corrected register names (added "USB" prefix as required) in Table 6-50, USB Control Registers..................... 85
• Added connection from "LCDS40...LCDS42" to AND gate in Figure 6-7, Port P5 (P5.2 to P5.7) Schematic .......... 96
• Added P7SEL.2 and XT2BYPASS inputs with AND and OR gates in Figure 6-10, Port P7 (P7.3) Schematic....... 100
• Changed P7SEL.3 column from X to 0 for "P7.3 (I/O)" rows ................................................................ 100
• Added Section 7 and moved Development Tools Support, Device and Development Tool Nomenclature,
Trademarks, and Electrostatic Discharge Caution sections to it ............................................................ 112
• Added Section 8, Mechanical, Packaging, and Orderable Information..................................................... 116
6
Revision History
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Product Folder Links: MSP430F6638 MSP430F6637 MSP430F6636 MSP430F6635 MSP430F6634 MSP430F6633
MSP430F6632 MSP430F6631 MSP430F6630