MSP430F6638 Datasheet, PDF (13/126 Pages) Texas Instruments – Mixed-Signal Microcontrollers

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MSP430F6638, MSP430F6637, MSP430F6636, MSP430F6635
MSP430F6634, MSP430F6633, MSP430F6632, MSP430F6631, MSP430F6630
SLAS566E – JUNE 2010 – REVISED DECEMBER 2015
AVSS1
XIN
XOUT
AVSS2
TERMINAL
NAME
P5.6/ADC12CLK/DMAE0
P2.0/P2MAP0
P2.1/P2MAP1
P2.2/P2MAP2
P2.3/P2MAP3
P2.4/P2MAP4
P2.5/P2MAP5
P2.6/P2MAP6/R03
P2.7/P2MAP7/LCDREF/R13
DVCC1
DVSS1
VCORE ⁽²⁾
P5.2/R23
LCDCAP/R33
COM0
P5.3/COM1/S42
P5.4/COM2/S41
Table 4-1. Signal Descriptions (continued)
NO.
I/O ⁽¹⁾
DESCRIPTION
PZ ZQW
12 F2
Analog ground supply
13 F1 I Input terminal for crystal oscillator XT1
14 G1 O Output terminal of crystal oscillator XT1
15 G2
Analog ground supply
General-purpose digital I/O
16 H1 I/O Conversion clock output ADC (not available on F6632, F6631, and F6630 devices)
DMA external trigger input
General-purpose digital I/O with port interrupt and mappable secondary function
17 G4 I/O
Default mapping: USCI_B0 SPI slave transmit enable; USCI_A0 clock input/output
General-purpose digital I/O with port interrupt and mappable secondary function
18 H2 I/O
Default mapping: USCI_B0 SPI slave in/master out; USCI_B0 I²C data
General-purpose digital I/O with port interrupt and mappable secondary function
19 J1 I/O
Default mapping: USCI_B0 SPI slave out/master in; USCI_B0 I²C clock
General-purpose digital I/O with port interrupt and mappable secondary function
20 H4 I/O
Default mapping: USCI_B0 clock input/output; USCI_A0 SPI slave transmit enable
General-purpose digital I/O with port interrupt and mappable secondary function
21 J2 I/O
Default mapping: USCI_A0 UART transmit data; USCI_A0 SPI slave in/master out
General-purpose digital I/O with port interrupt and mappable secondary function
22 K1 I/O
Default mapping: USCI_A0 UART receive data; USCI_A0 slave out/master in
General-purpose digital I/O with port interrupt and mappable secondary function
23 K2 I/O Default mapping: no secondary function
Input/output port of lowest analog LCD voltage (V5)
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: no secondary function
24 L2 I/O
External reference voltage input for regulated LCD voltage
Input/output port of third most positive analog LCD voltage (V3 or V4)
25 L1
Digital power supply
26 M1
Digital ground supply
27 M2
Regulated core power supply (internal use only, no external current loading)
General-purpose digital I/O
28 L3 I/O
Input/output port of second most positive analog LCD voltage (V2)
LCD capacitor connection
29 M3 I/O Input/output port of most positive analog LCD voltage (V1)
CAUTION: LCDCAP/R33 must be connected to DV_SS if not used.
30 J4 O LCD common output COM0 for LCD backplane
General-purpose digital I/O
31 L4 I/O LCD common output COM1 for LCD backplane
LCD segment output S42
General-purpose digital I/O
32 M4 I/O LCD common output COM2 for LCD backplane
LCD segment output S41
(2) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended
capacitor value, C_VCORE.
Copyright © 2010–2015, Texas Instruments Incorporated
Terminal Configuration and Functions
13
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MSP430F6632 MSP430F6631 MSP430F6630